TI工程师您好：
我在使用TCI6638EVM板跑TI提供的例子时，导入的Gel文件是mcsdk_bios_3_01_01_04\tools\program_evm\gel\xtcievmk2x.gel文件，打开gel文件想修改DDR3的时钟速率，在gel文件中查看DDRA和DDRB时钟速率配置函数
/*----------------------------------------------------- DDR3A : DDR1333, 32bit--------------------------------------------------------------------------*/
ddr3A_32bit_DDR1333_setup()
{
unsigned int multiplier = 19;
unsigned int divider = 0;
int temp;s
unsigned int OD_val = 6;
KICK0 = 0x83E70B13;
KICK1 = 0x95A4F1E0;
//1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
do {
read_val = DDR3A_PGSR0;
} while ((read_val&0x00000001) != 0x00000001);
//4. Clocks are enabled and frequency is stable---------------------------------------
//DDR3A PLL setup
GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
//DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF;
// Set ENSAT = 1
DDR3APLLCTL1 |= 0x00000040;
// Put the PLL in PLL Mode
DDR3APLLCTL0 |= 0x00800000;
// In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register)
DDR3APLLCTL1 |= 0x00002000;
// Program the necessary multipliers/dividers and BW adjustments
// Set the divider values
DDR3APLLCTL0 &= ~(0x0000003F);
DDR3APLLCTL0 |= (divider & 0x0000003F);
/* Step 7: Programming OD[3:0] in the SECCTL register */
DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
/* Set the Multipler values */
DDR3APLLCTL0 &= ~(0x0007FFC0);
DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
temp = ((multiplier + 1) >> 1) - 1;
DDR3APLLCTL0 &= ~(0xFF000000);
DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000);
DDR3APLLCTL1 &= ~(0x0000000F);
DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F);
//In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset
DDR3APLLCTL1 &= ~(0x00002000);
// Put the PLL in PLL Mode
DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.\n" );
//DDR3A PLL setup complete ---------------------------------------
*----------------------------------------------------- DDR3B : DDR1600, 64bit--------------------------------------------------------------------------*/
ddr3B_64bit_DDR1600_setup()
{
unsigned int multiplier = 15;
unsigned int divider = 0;
int temp;
unsigned int OD_val = 4;
KICK0 = 0x83E70B13;
KICK1 = 0x95A4F1E0;
//1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
do {
read_val = DDR3B_PGSR0;
} while ((read_val&0x00000001) != 0x00000001);
//4. Clocks are enabled and frequency is stable---------------------------------------
//DDR3B PLL setup
GEL_TextOut ( "DDR3 PLL Setup ... \n");
//DDR3BPLLCTL0 = DDR3BPLLCTL0 & 0xFF7FFFFF;
// Set ENSAT = 1
DDR3BPLLCTL1 |= 0x00000040;
// Put the PLL in PLL Mode
DDR3BPLLCTL0 |= 0x00800000;
// In PLL Controller, reset the PLL (bit 13 in DDR3BPLLCTL1 register)
DDR3BPLLCTL1 |= 0x00002000;
// Program the necessary multipliers/dividers and BW adjustments
// Set the divider values
DDR3BPLLCTL0 &= ~(0x0000003F);
DDR3BPLLCTL0 |= (divider & 0x0000003F);
/* Step 7: Programming OD[3:0] in the SECCTL register */
DDR3BPLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
DDR3BPLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
//DDR3BPLLCTL0 &= ~(0x00780000);
//DDR3BPLLCTL0 |= ((OD_val << 19)& 0x00780000);
/* Set the Multipler values */
DDR3BPLLCTL0 &= ~(0x0007FFC0);
DDR3BPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
temp = ((multiplier + 1) >> 1) - 1;
DDR3BPLLCTL0 &= ~(0xFF000000);
DDR3BPLLCTL0 |= ((temp << 24) & 0xFF000000);
DDR3BPLLCTL1 &= ~(0x0000000F);
DDR3BPLLCTL1 |= ((temp >> 8) & 0x0000000F);
//In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset
DDR3BPLLCTL1 &= ~(0x00002000);
// Put the PLL in PLL Mode
DDR3BPLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
GEL_TextOut( "DDR3 PLL Setup complete, DDR3B clock now running at 800MHz.\n" );
//DDR3B PLL setup complete ---------------------------------------
现在有3个疑问：
1.按照上面gel文件中提取出来的函数DDR3A、DDR3B跑的时钟速率分别是666Mhz、800MHz还是1333Mhz、1600Mhz？因为从函数命名的自注释来看
DDR3A的函数名ddr3A_32bit_DDR1333_setup，这个不就应该是要配置1333Mhz吗？ 但是打印时GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.\n" );又说该函数运行在666Mhz。
2.我想知道C6638芯片的DDR3时钟速率计算公式是什么？在6638数据手册上找到的唯一一个计算PLL时钟速率的公式为：
CLK = CLKIN*(PLLM+1)/((OUTPUT_DIVIDE+1)*(PLLD+1)) 如果按照这个来计算DDR3A CLK= 100Mhz*（19+1）/ ((6-1)+1)*(0+1)) =333.33Mhz，而DDR的时钟
速率是双时钟的，所以计算结果还要X2=666.67MHz, 如果第一个问题确认这个函数配置是666Mhz则问题2是不是就是按照我提到的这个公式来计算的？
3.另外我想知道如果我要增大DDR3的时钟速率，是不是在这2个函数中直接修改multiplier 、divider 、OD_val 这三个参数的值就行了，还用做其他改动吗？
谢谢您的解答~