DM8168走DVRRDK程序，是否有办法让某个SATA口上电默认强制为1.5Gbps?

SATA初始化的时候通常会协商来确定速率。这个一般都是在设备端决定，比如SATA接口硬盘上常见有跳线来决定速率。

你需要在主芯片端强制设定速率是基于什么样的场景？

我们让8168和SATA扩展器SII3826连接，然后发现有的时候，内核一上来很快就会打印

ata1: establish at 3Gbps....

类似的，就是以3Gbps建立连接，

有的时候就会不是很早显示这句话，而是先显示诸如：

ata1:soft reset failed(device not ready)

然后最终会以1.5Gbps连接。

所以我们怀疑是SATA高速线信号完整性不好，就想一上来就是1.5G.

一上来是3G，连sii3826,可能连不上，然后软件复位，就会耽误很长时间，影响我们进文件系统后判断设备是否成功连接。1.5G对我们应用来说是够的，因为后端SATA实际设备也是1.5G的。

To program 1.5Gbps from DM816x SATA side, see bits P#PHYCR[4:1] MPY

100MHz input frequency requirement is dependent upon the supported PHY PLL multiplier value. A single PLL within the SERDES device exists that is shared amongst the two HBA Ports. The control for this PLL and PHY operation is done via P0PHYCR register. That is, the programming done for the clock setting using Port 0 PHY Control Register applies to both ports and the respective field within P1PHYCR is reserved. See P#PHYCR (# = 0 or 1) register field descriptions for more detail. The MPY field of the P0PHYCR register is programmed with the PLL multiplier value based on the input frequency clock. Note that the PHY PLL output frequency should be exactly 1.5GHz (for both 3 and 1.5 Gbits/second line rate) and its accuracy is very important to the operation of the SATA controller.

Table 20-1 shows the MPY bit field of P#PHYCR for supported PHY PLL multiplier values.

Configure the PHY using the port PHY control register (P#PHYCR):
(a) Set the MPY bit field for the PLL multiply factor (multiply value selected should target a 1.5-GHz frequency that is good enough for both GEN1 and GEN2 speeds).

Check also P#SSTS[7:4] SPD to see the speed set.

P#SCTL[7:4] SPD = 0x1 for 1.5Gbps mode

Check also use case in TRM:

#define DESIRED_SPEED (GEN1) // GOASFASTASDEVICE, GEN1, GEN2

// Configure Line Speed.
setSataSpeed(DESIRED_SPEED);

void setSataSpeed(unsigned char iSpeed) {
sataRegs->P0SCTL |= (iSpeed << AHCI_PxSCTL_PxSSTS_SPD_SHIFT);
waitForXms(5); // This might not be necessary: wait a bit
}