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DM368 VPBE LCD输出问题



目前我司使用DM368 VPBE LCD控制器显示图像,发现其CLK、DATA输出为标准的下降沿采样时序,是否有寄存器配置可以调整CLK的输出相位,使CLK的上升沿提前几ns?我们已经尝试修改寄存器DCLKCTL.DOFST,但是没有任何效果;