在对tms320C6747 PLL配置时,PLLDIV2默认值为1,若修改为其他值,就会报错,而且仿真器也连不上,请问问题出在哪?
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在对tms320C6747 PLL配置时,PLLDIV2默认值为1,若修改为其他值,就会报错,而且仿真器也连不上,请问问题出在哪?
C674X_0: Trouble Halting Target CPU: (Error -1060 @ 0x0) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.569.0)
以上是程序暂停后的报错信息
仿真器是SEED-XDS560V2
CCS版本是Code composer studio V5
void InitPLL(void)
{
int i = 0;
Uint8 CLKMODE = 1; //方波
Uint8 PLLM = 19; //25*(19+1)=500M
Uint8 POSTDIV = 1; // clk_M / 2 = 250M
Uint8 PLLDIV2 = 1;
Uint8 PLLDIV3 = 2; //250/3=83M
Uint8 PLLDIV5 = 5;
Uint8 PLLDIV7 = 7;
Uint8 PREDIV = 0;
PLL0_PLLCTL &= 0xFFFFFFFE;
for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}
PLL0_PLLCTL &= 0xFFFFFEFF;
PLL0_PLLCTL |= (CLKMODE<<8);
PLL0_PLLCTL &= 0xFFFFFFDF;
PLL0_PLLCTL &= 0xFFFFFDFF;
PLL0_PLLCTL &= 0xFFFFFFF7;
PLL0_PLLCTL |= 0x10;
PLL0_PLLCTL &= 0xFFFFFFFD;
PLL0_PLLCTL &= 0xFFFFFFEF;
PLL0_PREDIV = 0x8000 | PREDIV;
PLL0_PLLM = PLLM; /* Make PLLMULTIPLEIR as bootpacket*/
PLL0_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/
while(PLL0_PLLSTAT & 0x1==1){}
PLL0_PLLDIV2 = 0x8000 | PLLDIV2;
PLL0_PLLDIV3 = 0x8000 | PLLDIV3; /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/
PLL0_PLLDIV5 = 0x8000 | PLLDIV5; /* Make PLLDIV5 as bootpacket, do it for other PLLDIVx to if required*/
PLL0_PLLDIV7 = 0x8000 | PLLDIV7; /* Make PLLDIV7 as bootpacket, do it for other PLLDIVx to if required*/
PLL0_PLLCMD |= 0x1;
while(PLL0_PLLSTAT & 0x1==1) { }
PLL0_PLLCTL |= 0x8;
for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;}
PLL0_PLLCTL |= 0x1;
KICK0R = 0x83e70b13; // Kick0 register + data (unlock)
KICK1R = 0x95a4f1e0; // Kick1 register + data (unlock)
}
PLLDIV2值是固定的,不能改。在下面的TRM上有说明, PLLDIV1, PLLDIV2, PLLDIV4都不能改。
Table 6-2. System Clock Domains
http://www.ti.com/lit/ug/spruh91b/spruh91b.pdf