EVM6657LS boot 多核的问题 (with IBL)

Lin Jia-Hung

你好, 花好了几天, 试了许多Boot方法, 都无法启动C6657 双核心.

两核心都是使用相同的程序代码, 依不同Core执行各自程序代码, 此程序已在Debug下验证过了.

int main(void)
{
    Uint32 coreNum = 0xFFFF;
	coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
    if (coreNum == 0)
    {
        func1(); // send UART message
    }
    else
    {
        func2();
    }
}

目前有效启动C6657的方式是将Myproj\Debug\app.bin (675kB)

取代放置于C:\ti\mcsdk_2_01_02_06\tools\program_evm\binaries\evm6657l\nor.bin

再利用program_evm将程序代码写入I2C EEPROM及Nor Flash

> %DSS_SCRIPT_DIR%/dss.bat program_evm.js tmdsevm6657ls-le

设定I2C Boot

SW3 (off off on off on on on on) SW5 (on on on off on on on on) SW9 (on on)

可以利用UART确定core 0结果正确, 再将两Core所要执行程序代码互换, Core1所要列出之UART并无法输出,表示core1无法启动或有设定有错.

Q.想请教要如何启动Core1或所需要之设定? 是否可以修改IBL使得启动Core 0及Core1.

谢谢

10 年多前

0 Allen35065 10 年多前

TI__Mastermind 27075 points

见Datasheet和Bootloader的手册，启动第二个核需要写core 1的Magic Address和发送IPC中断，这个流程和RBL启动没有区别。

至于这个操作是放在core 0的main函数还是IBL做就取决于你的需求了，原理上都可以，在core 0上做会简单点，不用改IBL。

0 Lin Jia-Hung 10 年多前回复 Allen35065

Prodigy 190 points

你好, 你的回答有效解决我的问题

并参考了程序代码 https://github.com/sfwa/fcs/blob/master/fcs/hardware/core/c6657.c

在Core0程序上加入Magic Address以及发送IPC, 可以启动C6657 Core 1

if (coreNum == 0)
{
    CSL_BootCfgUnlockKicker();
    // IPC generation
    /*
    Start booting core 1:
    - Copy all code/data in CorePac 0 L2 to CorePac 1 L2
    - Populate BOOT_MAGIC_ADDRESS for CorePac 1, which should be the same as
      for CorePac 0.
    - Send an IPC interrupt to CorePac 1 (IPCGR1.IPCG) to wake it up.
    */
    memcpy(
        (uint8_t*)GLOBAL_FROM_CORE_L2_ADDRESS(1u, 0x00800000u),
        (uint8_t*)0x00800000u,
        0x000F0000u
    );

    /*
    0x008FFFFCu is the boot magic address for the local core (it's at the end
    of L2 SRAM). Here, we convert that local address for CorePac 1's L2 SRAM
    to a global address, then copy the value of CorePac 0's boot magic address
    to it.
    */
    *(volatile uint32_t*)(GLOBAL_FROM_CORE_L2_ADDRESS(1u, 0x008FFFFCu)) =
        (uint32_t)_c_int00;

    /*
    IPCGRn: IPC Generation Registers (section 3.3.12 in SPRS814A)
    Bit   Field          Value         Description
    31:4  SRCSx          0             Interrupt source indication
    3:1   Reserved
    0     IPCG           0             Generate an IPC interrupt
                                       0 = no interrupt
                                       1 = generate an interrupt
    Sending this interrupt wakes CorePac 1 up.
    */
    hBootCfg->IPCGR[1] |= 0x1u;
    /* Just in case the above is wrong */
    *(volatile uint32_t*)0x02620244 |= 0x1u;
    CSL_BootCfgLockKicker();
}

谢谢

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EVM6657LS boot 多核的问题 (with IBL)