1，In the application of TDA4VH, if all serdes signals of serdes0 bank are not used, can the serdes0_REFCLK signal of this bank be left floating?
2，When serdes1 bank is used as the PCIE0 X4 RC mode, does the SERDES1_REFCLK signal still need to input a 100M clock? Can the PCIE_REFCLK0 signal directly output a 100M clock to the EP device as a reference clock?
For 1, yes SERDES_REFCLK pins can be left open if unused.
For 2, it is configurable. Either SERDES1_REFCLK_P/N receives a clock, or PCIE_REFCLK0_P/N_OUT outputs a clock. Both would work for EP or RC. For example, on TI J784S4 EVM, PCIe1 on SERDES0 uses the internal reference clock from PCIE_REFCLK0_P/N_OUT to supply the connector a reference clock, while PCIe0 on SERDES1 receives an external reference clock on SERDES1_REFCLK_P/N.
