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Section 1.3 - "The C66x core can execute 8 single-precision floating-point MAC operations per cycle, perform double- and mixed-precision operations, and be IEEE 754 compliant."
Section 6.25 - "Each C66x .M unit also includes IEEE floating-point multiplication operations from the C674x DSP, which includes one single-precision multiply each cycle and one double-precision multiply every 4 cycles. There is also a mixed-precision multiply that allows multiplication of a single-precision value by a double-precision value and an operation allowing multiplication of two single-precision numbers resulting in a double-precision number. The C66x DSP improves the performance over the C674x double-precision multiplies by adding an instruction allowing one double-precision multiply per cycle and also reduces the number of delay slots from 10 down to 4. Each C66x .M unit can also perform one of the following floating-point operations each clock cycle: one, two, or four single-precision multiplies or a complex single-precision multiply."
