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DM6437 VPBE支持RGB888并行数字输出，请问应该怎么配置这一组寄存器，有相关的指导文档或例程（except DM643x VPBE user guid）不？
你好，
请问你是否有看过下面的文档和例子？
嗯，研究过的，但是并没有关于VENC RGB888 digital output的相关设置。以下是我的配置：
vencRegs = (CSL_VencRegs * )llcRegisterBaseAddr; /* Reset video encoder module */ //vencRegs->VMOD = 0; /* Reset video encoder module */ vencRegs->VMOD = 0x2013; /* Enable VCLK output, no inverted */ vencRegs->VIDCTL = 0x6000; /* Prefilter sampling frequency - Normal */ vencRegs->VDPRO = 0 | (1<< 11) | (0 << 8);//| (1 << 6)| (1 << 5); // Color Bar mode /* Set Timing */ /* VSPLS - Horizon Sync Pulse Width Configuration */ vencRegs->HSPLS = 220; vencRegs->HSTART = 120; vencRegs->HVALID = 1024; vencRegs->HINT = 1344; /* Vertical Sync Pulse Width Configuration */ vencRegs->VSPLS = 38; vencRegs->VSTART = 0; vencRegs->VVALID = 768; vencRegs->VINT = 806; vencRegs->HSDLY = 0; vencRegs->VSDLY = 0; vencRegs->YCCCTL = 0; /* HSYNC and VSYNC pulse, active low */ vencRegs->SYNCCTL = 0x03; /* YCbCr -> RGB convert matrix */ vencRegs->DRGBX0 = 0x00000400; vencRegs->DRGBX1 = 0x00000576; vencRegs->DRGBX2 = 0x00000159; vencRegs->DRGBX3 = 0x000002cb; vencRegs->DRGBX4 = 0x000006ee; /* Enable DCLK as clock enable for enc clock */ vencRegs->DCLKCTL = 0x0800; vencRegs->DCLKPTN0 = 1; vencRegs->DCLKPTN1 = 0; vencRegs->DCLKPTN2 = 0; vencRegs->DCLKPTN3 = 0; vencRegs->DCLKPTN0A = 2; vencRegs->DCLKPTN1A = 0; vencRegs->DCLKPTN2A = 0; vencRegs->DCLKPTN3A = 0; vencRegs->DCLKHS = 0; vencRegs->DCLKHSA = 1; vencRegs->DCLKHR = 0; vencRegs->DCLKVS = 0; vencRegs->DCLKVR = 0; vencRegs->BRTS = 0; vencRegs->BRTW = 0; vencRegs->ACCTL = 0; vencRegs->PWMP = 0; vencRegs->PWMW =0; vencRegs->CVBS = 0; vencRegs->CMPNT =0; vencRegs->LCDOUT = 0x01;
VIDWIN0:yuv422 1024*768*2
colorbar模式可以正常显示，视频有问题，哪里配置有问题，谢谢！
