Dear Engineer,
Hello! I have designed my own PCB using the AWR2243 chip and would like to configure the AWR2243 via an FPGA and receive signals from it. However, I get some errors when distributing the clock signal from the master chip to the slave chip. I would greatly appreciate your help.
I provide the master chip with a 40MHz, 1200mV AC signal. Currently, the master chip can be successfully configured, but the slave chip cannot communicate successfully. I have tested the AWR1_OSC_CLKOUT of the master chip used for distributing the clock signal, and its peak-to-peak value is about 400mV. The clock signal distributed to the slave chip, AWR2_XTAL_CLK, is approximately 1.7Vpp. Neither of these clock signal amplitudes falls within the external clock amplitude input range specified in your company's single datasheet (700-1200mV). Based on the current situation, I would like to ask you the following questions:
1. Is the reason that I cannot configure the slave chip due to the amplitude of the external clock signal?
2. If the reason that I cannot configure the slave chip is due to the amplitude of the external clock signal, could you explain why the AC signal provided can successfully configure the master chip but encounters amplitude errors when configuring the slave chip?
3. What should I do to improve this issue?
Thank you very much for your help.
