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AWR1843: lvds速率配置

qing zhang
Prodigy 70 points
Part Number: AWR1843

我们后级FPGA对于LVDS单lane的接收不能超过400Mb/s

TI板子的数据发需要单lane 350Mb/s才能及时传出去

目前看AWR18xx16xx14xx Technical Reference Manual(Rev.E) 15.3.1节描述，lvds 在300MHZ DDR Clock 之上是450MHZ DDR，lvds时钟能否配成350Mb/s？