IWR1843BOOST: 出现报错：out of L2 heap memory!

JESU LEE

Part Number: IWR1843BOOST
Other Parts Discussed in Thread: AWR1843

工程师你好，

描述：我上次提问的L2内存不足通过修改SOC_XWR18XX_DSS_L2_BUFF_SIZE大小可以通过编译；

#define SOC_XWR18XX_DSS_L2_SCRATCH_SIZE 0x2000U
#define SOC_XWR18XX_DSS_L2_BUFF_SIZE 0xB000U
//#define SOC_XWR18XX_DSS_L2_BUFF_SIZE 0xF000U

/*! L2 RAM buffer */
#pragma DATA_SECTION(gMmwL2, ".l2data");
#pragma DATA_ALIGN(gMmwL2, 8);
uint8_t gMmwL2[SOC_XWR18XX_DSS_L2_BUFF_SIZE];

/*! L2 RAM scratch */
#pragma DATA_SECTION(gMmwL2, ".l2data");
#pragma DATA_ALIGN(gMmwL2, 8);
uint8_t gMmwL2Scratch[SOC_XWR18XX_DSS_L2_SCRATCH_SIZE];

问题1：编译过的map文件显示还有内存，但如果改成0XF000就不行，请问这是什么原因？

问题2：但是运行程序时遇到以下问题，问题出现在创建变量空间上，使用的程序是将AWR1843的自动泊车程序；

程序运行到inst->detectionInstance = (void *) RADARDEMO_detectionCFAR_create(cfarConfig, &inst->cfarErrorCode);这个函数时，

出现out of L2 heap memory!报错，我认为是大小给定不足，但是通过修改SOC_XWR18XX_DSS_L2_BUFF_SIZE发现没有用，

请问这是什么问题呢？

2 年多前

0 Nancy Wang 2 年多前

TI__Guru** 110395 points

JESU LEE 说：
define SOC_XWR18XX_DSS_L2_BUFF_SIZE 0xF000U

这部分内容您是自己定义的吗？我在例程中没有找到。

JESU LEE 说：
但如果改成0XF000就不行，请问这是什么原因？

有什么报错吗？

l2data分配在哪里？将cmd附件上传看一下。

0 JESU LEE 2 年多前回复 Nancy Wang

Intellectual 270 points

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 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#define L1P_CACHE_SIZE (16*1024)
#define L1D_CACHE_SIZE (16*1024)
#define MMWAVE_L3RAM_SIZE (MMWAVE_L3RAM_NUM_BANK*MMWAVE_SHMEM_BANK_SIZE)

MEMORY
{
PAGE 0:

#if (L1P_CACHE_SIZE < 0x8000)
    L1PSRAM:        o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
#endif
#if (L1D_CACHE_SIZE < 0x8000)
    L1DSRAM:        o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
#endif
    L2SRAM_UMAP1:   o = 0x007E0000, l = 0x00020000
    L2SRAM_UMAP0:   o = 0x00800000, l = 0x00020000
    L3SRAM:         o = 0x20000000, l = MMWAVE_L3RAM_SIZE
    HWA_RAM :       o = 0x21030000, l = 0x00010000
    HSRAM:          o = 0x21080000, l = 0x8000

    /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
       Some examples:
       1. Overlay one-time only text with uninitialized data.
       2. Overlay L1PSRAM data path processing fast code and use copy tables
          to page in (before entering data path) and out of L1PSRAM (when entering
          sleep/low power).
    */
PAGE 1:
    L3SRAM:         o = 0x20000000, l = MMWAVE_L3RAM_SIZE
}

/* Set L1D, L1P and L2 Cache Sizes */
ti_sysbios_family_c64p_Cache_l1dSize = L1D_CACHE_SIZE;
ti_sysbios_family_c64p_Cache_l1pSize = L1P_CACHE_SIZE;
ti_sysbios_family_c64p_Cache_l2Size  = 0;

SECTIONS
{
    /* hard addresses forces vecs to be allocated there */
    .vecs:  {. = align(32); } > 0x007E0000

    /* Allocate data preferentially in one UMAP and code (.text) in another,
       this can improve performance due to simultaneous misses from L1P
       and L1D caches to L2 SRAM, for more information see C674 Megamodule
       User Guide section "Level 2 Memory Architecture".
       The linker notation "X >> Y | Z" indicates section X is first allocated in Y
       and allowed to overflow into Z and can be split from Y to Z.
       The linker notation "X > Y | Z" indicates section X is first allocated in Y
       and allowed to overflow into Z and cannot be split from Y to Z. Some sections
       like bss are not allowed to be split so > notation is used for them */

    .fardata:  {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
    .const:    {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
    .switch:   {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
    .cio:      {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
    .data:     {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1

    .rodata:   {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
    .bss:      {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
    .neardata: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
    .stack:    {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
    .cinit:    {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
    .far:      {} > L2SRAM_UMAP0 | L2SRAM_UMAP1

    .text: {} >> L2SRAM_UMAP1 | L2SRAM_UMAP0
}

/*----------------------------------------------------------------------------*/
/* Linker Settings                                                            */
--retain="*(.intvecs)"

--stack_size=0x1000

/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */
-ldsplib.ae64P
-llibmmwavealg_xwr18xx.ae674
-lmathlib.ae674
-llibsoc_xwr18xx.ae674
SECTIONS
{
    systemHeap : {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
    .l2data : {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1

    /* HSRAM has output data from processing chain running on DSP */
    .demoSharedMem > HSRAM

    /* L3SRAM has code that is overlaid with data, so data must be
       marked uninitialized. Application can initialize this section
       using _L3data_* symbols defined below. Code should be written carefully as
       these are linker symbols (see for example http://e2e.ti.com/support/development_tools/compiler/f/343/t/92002 ):

        extern far uint8_t _L3data_start; // the type here does not matter
        extern far uint8_t _L3data_size;  // the type here does not matter

        memset((void *)_symval(&_L3data_start), 0, (uint32_t) _symval(&_L3data_size));
    */
    .l3data: type=NOINIT, start(_L3data_start), size(_L3data_size), load=L3SRAM PAGE 1

    /* Bootloader cannot load L1DSRAM, make sure to mark as NOINIT */
    .l1data : type=NOINIT, load=L1DSRAM



    /* Currently bootloader does not allow loading in L1PSRAM because of supporting
       low power. Below fast code is loaded in L3SRAM but run from L1PSRAM. The copy-in
       is called during initialization phase and copy-out is not used but can be added when
       supporting low-power mode (where L1 contents are not retained).
     */
    .fastCode:
    {
        dsplib.ae64P(.text)
        libmmwavealg_xwr18xx.ae674(.text)
        //mathlib.ae674(.text)
        //dss_data_path.oe674(.text:secondDimFFTandLog2Computation)
        dss_data_path.oe674(.text:MmwDemo_processChirp)
        dss_data_path.oe674(.text:MmwDemo_interChirpProcessing)
        //dss_data_path.oe674(.text:MmwDemo_XYestimation)
        //dss_data_path.oe674(.text:cfarCa_SO_dBwrap_withSNR)
        //dss_data_path.oe674(.text:cfarCadB_SO_withSNR)
        /*dss_data_path.oe674(.text:cfarPeakGroupingAlongDoppler)
        dss_data_path.oe674(.text:pruneToPeaks)
        dss_data_path.oe674(.text:findKLargestPeaks)
        dss_data_path.oe674(.text:disambiguateVel)
        dss_data_path.oe674(.text:MmwDemo_setDopplerLine)
        dss_data_path.oe674(.text:MmwDemo_getDopplerLine)
        */
        //dss_data_path.oe674(.text:rangeBasedPruning)
       /* dss_data_path.oe674(.text:MmwDemo_magnitudeSquared)*/
        //dss_data_path.oe674(.text:azimuthProcessing)
        dss_data_path.oe674(.text:MmwDemo_waitEndOfChirps)
        //clusteringDBscan.oe674(.text:clusteringDBscan_findNeighbors2Fixed)
        //Extended_Kalman_Filter_xyz.oe674(.text:isTargetWithinDataAssociationThresh)
    } load=L3SRAM PAGE 0, run=L1PSRAM PAGE 0, table(_MmwDemo_fastCode_L1PSRAM_copy_table, compression=off)

    /* This is auto generated by linker related to copy table above */
    .ovly > L2SRAM_UMAP0 | L2SRAM_UMAP1

    /* Overlay one-time/init-time (and non-critical in cycles) with L3 data,
       will be erased during data path processing. Note do not put any
       code that is required related to start/stop/reconfig processing */

    .overlay:
    {
    //    libsoc_xwr18xx.ae674 (.text:SOC_init)
    //    dss_main.oe674 (.text:main)
    //    dss_main.oe674 (.text:MmwDemo_populateMRR)
    //    dss_main.oe674 (.text:MmwDemo_populateUSRR)
        dss_data_path.oe674 (.text:MmwDemo_dataPathInitEdma)
    } > L3SRAM PAGE 0

}
/*----------------------------------------------------------------------------*/

0 JESU LEE 2 年多前回复 Nancy Wang

Intellectual 270 points

Nancy Wang 说：
这部分内容您是自己定义的吗？我在例程中没有找到。

这个是参照pa_18xx_dss的 dss_data_path.c文件改的，原来的就是0XF000，

我改成0XB000

0 Jack 2 年多前

Intellectual 535 points

你好，我是路人。我怎么看你发的代码15行和16行那里是不是有冲突？15行L2起始地址007e0000，长度00020000，也就是尾地址00810000？而16行L2起始地址是00800000，会不会有冲突？我是小白，个人感觉而已。

0 JESU LEE 2 年多前回复 Jack

Intellectual 270 points

你好，上面那张图我发的是map文件，是显示内存大小的，编译后的结果，应该不会出错

0 Nancy Wang 2 年多前回复 JESU LEE

TI__Guru** 110395 points

我稍后看一下再给您回复。

0 Nancy Wang 2 年多前回复 JESU LEE

TI__Guru** 110395 points

MMW_L2_HEAP_SIZE大小修改重定义看看。

#define MMW_L2_HEAP_SIZE 0x11000U

0 JESU LEE 2 年多前回复 Nancy Wang

Intellectual 270 points

这样改的话编译会出错，是不是代码量太大了，您编译成功了吗

<Linking>
"../dss_mmw_linker.cmd", line 44: warning #10068-D: no matching section
"../c674x_linker.cmd", line 83: error #10099-D: program will not fit into available memory.  placement with alignment fails for section ".fardata" size 0x1414 .  Available memory ranges:
   L2SRAM_UMAP0   size: 0x20000      unused: 0x8          max hole: 0x7       
   L2SRAM_UMAP1   size: 0x20000      unused: 0x0          max hole: 0x0       
"../dss_mmw_linker.cmd", line 11: error #10099-D: program will not fit into available memory.  run placement with alignment fails for section "systemHeap" size 0x4007 .  Available memory ranges:
   L2SRAM_UMAP0   size: 0x20000      unused: 0x8          max hole: 0x7       
   L2SRAM_UMAP1   size: 0x20000      unused: 0x0          max hole: 0x0       
"../c674x_linker.cmd", line 94: error #10099-D: program will not fit into available memory.  run placement with alignment fails for section ".far" size 0x3158 .  Available memory ranges:
   L2SRAM_UMAP0   size: 0x20000      unused: 0x8          max hole: 0x7       
   L2SRAM_UMAP1   size: 0x20000      unused: 0x0          max hole: 0x0       
"../c674x_linker.cmd", line 92: error #10099-D: program will not fit into available memory.  run placement with alignment fails for section ".stack" size 0x418 .  Available memory ranges:
   L2SRAM_UMAP0   size: 0x20000      unused: 0x8          max hole: 0x7       
   L2SRAM_UMAP1   size: 0x20000      unused: 0x0          max hole: 0x0       
"../c674x_linker.cmd", line 85: error #10099-D: program will not fit into available memory.  placement with alignment fails for section ".switch" size 0x1aa .  Available memory ranges:
   L2SRAM_UMAP0   size: 0x20000      unused: 0x8          max hole: 0x7       
   L2SRAM_UMAP1   size: 0x20000      unused: 0x0          max hole: 0x0       
"../c674x_linker.cmd", line 86: error #10099-D: program will not fit into available memory.  run placement with alignment fails for section ".cio" size 0x127 .  Available memory ranges:
   L2SRAM_UMAP0   size: 0x20000      unused: 0x8          max hole: 0x7       
   L2SRAM_UMAP1   size: 0x20000      unused: 0x0          max hole: 0x0       
"../c674x_linker.cmd", line 91: error #10099-D: program will not fit into available memory.  placement with alignment fails for section ".neardata" size 0xc .  Available memory ranges:
   L2SRAM_UMAP0   size: 0x20000      unused: 0x8          max hole: 0x7       
   L2SRAM_UMAP1   size: 0x20000      unused: 0x0          max hole: 0x0       
"../dss_mmw_linker.cmd", line 56: error #10099-D: program will not fit into available memory.  placement with alignment fails for section ".ovly" size 0x10 .  Available memory ranges:
   L2SRAM_UMAP0   size: 0x20000      unused: 0x7          max hole: 0x7       
   L2SRAM_UMAP1   size: 0x20000      unused: 0x0          max hole: 0x0       
error #10010: errors encountered during linking; "radar_18xx_dss_v1.9.xe674" not built
 
>> Compilation failure
makefile:191: recipe for target 'radar_18xx_dss_v1.9.xe674' failed
gmake[2]: *** [radar_18xx_dss_v1.9.xe674] Error 1
makefile:187: recipe for target 'main-build' failed
gmake[1]: *** [main-build] Error 2
makefile:182: recipe for target 'all' failed
gmake: *** [all] Error 2

**** Build Finished ****

0 Nancy Wang 2 年多前回复 JESU LEE

TI__Guru** 110395 points

JESU LEE 说：
这样改的话编译会出错

你是重定义了MMW_L2_HEAP_SIZE 就出现如上的报错吗？我在例程上修改了没有报错。

0 JESU LEE 2 年多前回复 Nancy Wang

Intellectual 270 points

感谢回复，方便将例程发一下吗

0 Nancy Wang 2 年多前回复 JESU LEE

TI__Guru** 110395 points

就是在您使用的pa例程上测试的。

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IWR1843BOOST: 出现报错：out of L2 heap memory!

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IWR1843BOOST: 出现报错：out of L2 heap memory!