Hi
Generally, access to critical section resources is accomplished by enabled and disabled interrupts.
For example, the R5F and DSP access the critical section simultaneously, Obviously, enbling and disabling interrupts is no longer suitable.
In the ARM architecture, the R5F is a dual-core lockstep processor. If set to non-lockstep mode,
there is an exclusive method for multi-core access to the critical section, which can drive hardware to achieve exclusive access.
Does the DSP have a similar design to the R5F? If so, what is the reference documentation, or are there any good solutions to this problem?
