请教一下，规格书上说如果不使用内部DCDC，VDDR接的就是内部LDO。那怎么判断芯片是使用内部DCDC还是内部LDO呢，是芯片自动感应，还是外面人为设置 ？
谢谢！
请教一下，规格书上说如果不使用内部DCDC，VDDR接的就是内部LDO。那怎么判断芯片是使用内部DCDC还是内部LDO呢，是芯片自动感应，还是外面人为设置 ？
谢谢！
用Jlink方式也试过，接线如附图
我还是有个疑问，6.3节上说Vddr要么是从DCDC来，要么是从globle LDO来。从1.3.13.1节中的截图来看，似乎默认还是从globle LDO来的。难道此截图有误，Vddr实际是默认的是从DCDC来的 ？
Maximum efficiency is obtained by using the internal DC/DC converter, and it requires an external inductor
(LDCDC) and capacitor (CDCDC). The components should be placed as close as possible to the
CC13xx/CC26xx device and it is important to have a short current return path for from the CDCDC ground
to the pad on the chip (see Section 4.7). In addition, the bulk capacitor on VDDS should be placed close
to the VDDS_DCDC-pin. The actual value of LDCDC, CDCDC and CBULK vary from device to device.
For the actual values, see the device-specific reference design.
When operating in DC/DC mode, the power system dynamically switches between the Global LDO and
DC/DC converter depending on the required load to achieve maximum efficiency. If VDDS drops below
2.0 V, the DC/DC converter will be less efficient than the LDO and the device will run in global LDO mode.
For systems operating with VDDS less than 2.0 V, consider either global LDO or external regulator mode
to save component cost and board area.
