1. 发纯载波，怎么做？
2. GDO0 始终无法正常工作（主设备GDO0输入模式正常，我是没招了，希望这儿能得到答案！）
寄存器配置如下：
spi_write_reg(CCxxx0_IOCFG2, 0x29); // GDO2 output pin config.
spi_write_reg(CCxxx0_IOCFG0, 0x06); // PIN_GDO0 output pin config.
spi_write_reg(CCxxx0_PKTLEN, 0xff); // 06 Packet length.
spi_write_reg(CCxxx0_FSCTRL1, 0x12); // 0b Freq synthesizer control.
spi_write_reg(CCxxx0_FSCTRL0, 0x00); // 0c Freq synthesizer control.
spi_write_reg(CCxxx0_PKTCTRL1, 0x04); // 07 Packet automation control.
spi_write_reg(CCxxx0_PKTCTRL0, 0x05); // 08 Packet automation control.
spi_write_reg(CCxxx0_CHANNR, 0x00); // 0a Channel number.
spi_write_reg(CCxxx0_FREQ2, 0x5d); // 0d Freq control word, high byte.
spi_write_reg(CCxxx0_FREQ1, 0x93); // 0e Freq control word, mid byte.
spi_write_reg(CCxxx0_FREQ0, 0xb1); // 0f Freq control word, low byte.
spi_write_reg(CCxxx0_FSCAL3, 0xea); // 23 Frequency synthesizer cal.
spi_write_reg(CCxxx0_FSCAL2, 0x0a); // 24 Frequency synthesizer cal.
spi_write_reg(CCxxx0_FSCAL1, 0x00); // 25 Frequency synthesizer cal.
spi_write_reg(CCxxx0_FSCAL0, 0x11); // 26 Frequency synthesizer cal.
spi_write_reg(CCxxx0_FSTEST, 0x59); // 29 Frequency synthesizer cal.
spi_write_reg(CCxxx0_MDMCFG4, 0x2d); // 10 Modem configuration.
spi_write_reg(CCxxx0_MDMCFG3, 0x3b); // 11 Modem configuration.
spi_write_reg(CCxxx0_MDMCFG2, 0xf3); // 12 Modem configuration.
spi_write_reg(CCxxx0_MDMCFG1, 0x22); // 13 Modem configuration.
spi_write_reg(CCxxx0_MDMCFG0, 0xf8); // 14 Modem configuration.
spi_write_reg(CCxxx0_DEVIATN, 0x00); // 15 Modem dev (when FSK mod en)
spi_write_reg(CCxxx0_FREND1, 0xb6); // 21 Front end RX configuration.
spi_write_reg(CCxxx0_FREND0, 0x10); // 22 Front end RX configuration.
spi_write_reg(CCxxx0_FOCCFG, 0x1d); // 19 Freq Offset Compens. Config
spi_write_reg(CCxxx0_BSCFG, 0x1c); // 1a Bit synchronization config.
spi_write_reg(CCxxx0_AGCCTRL2, 0xc7); // 1b AGC control.
spi_write_reg(CCxxx0_AGCCTRL1, 0x00); // 1c AGC control.
spi_write_reg(CCxxx0_AGCCTRL0, 0xB0); // 1d AGC control.
spi_write_reg(CCxxx0_MCSM1, 0x3f); // 17 MainRadio Cntrl State Machine
spi_write_reg(CCxxx0_MCSM0, 0x18); // 18 MainRadio Cntrl State Machine
spi_write_reg(CCxxx0_TEST2, 0x88); // 2c Various test settings.
spi_write_reg(CCxxx0_TEST1, 0x31); // 2d Various test settings.
spi_write_reg(CCxxx0_TEST0, 0x0b); // 2e Various test settings.
spi_write_reg(CCxxx0_FIFOTHR, 0x07); // FIFOTHR RXFIFO and TXFIFO thresholds.
spi_write_reg(CCxxx0_ADDR, 0x00); // 09 Device address.
