CC1120: 在接收模式下，即使没有射频信号存在，RSSI值也很高

// Address Config = Address check, no broadcast 
// Bit Rate = 50 
// Carrier Frequency = 434.000000 
// Deviation = 24.963379 
// Device Address = 0 
// Manchester Enable = false 
// Modulation Format = 2-GFSK 
// PA Ramping = true 
// Packet Bit Length = 0 
// Packet Length = 24 
// Packet Length Mode = Variable 
// Performance Mode = High Performance 
// RX Filter BW = 100.000000 
// Symbol rate = 50 
// TX Power = 15 
// Whitening = true 
#include "stdint.h"
const uint16_t CC112X_REG_SETTING[][2]= 
{
 {0X0000,0X53},//IOCFG3             GPIO3 IO PIN CONFIGURATION
 {0X0001,0X46},//IOCFG2             GPIO2 IO PIN CONFIGURATION
 {0X0003,0X51},//IOCFG0             GPIO0 IO PIN CONFIGURATION
 {0X0008,0X08},//SYNC_CFG1          SYNC WORD DETECTION CONFIGURATION REG. 1
 {0X000A,0X99},//DEVIATION_M        FREQUENCY DEVIATION CONFIGURATION
 {0X000B,0X0D},//MODCFG_DEV_E       MODULATION FORMAT AND FREQUENCY DEVIATION CONFIGUR..
 {0X000C,0X15},//DCFILT_CFG         DIGITAL DC REMOVAL CONFIGURATION
 {0X000D,0X18},//PREAMBLE_CFG1      PREAMBLE LENGTH CONFIGURATION REG. 1
 {0X000F,0X3A},//FREQ_IF_CFG        RX MIXER FREQUENCY CONFIGURATION
 {0X0010,0X00},//IQIC               DIGITAL IMAGE CHANNEL COMPENSATION CONFIGURATION
 {0X0011,0X02},//CHAN_BW            CHANNEL FILTER CONFIGURATION
 {0X0013,0X05},//MDMCFG0            GENERAL MODEM PARAMETER CONFIGURATION REG. 0
 {0X0014,0X99},//SYMBOL_RATE2       SYMBOL RATE CONFIGURATION EXPONENT AND MANTISSA [1..
 {0X0015,0X99},//SYMBOL_RATE1       SYMBOL RATE CONFIGURATION MANTISSA [15:8]
 {0X0016,0X99},//SYMBOL_RATE0       SYMBOL RATE CONFIGURATION MANTISSA [7:0]
 {0X0017,0X3C},//AGC_REF            AGC REFERENCE LEVEL CONFIGURATION
 {0X0018,0XA1},//AGC_CS_THR         CARRIER SENSE THRESHOLD CONFIGURATION
 {0X0019,0X9A},//AGC_GAIN_ADJUST    RSSI OFFSET CONFIGURATION
 {0X001C,0XA9},//AGC_CFG1           AUTOMATIC GAIN CONTROL CONFIGURATION REG. 1
 {0X001D,0XC0},//AGC_CFG0           AUTOMATIC GAIN CONTROL CONFIGURATION REG. 0
 {0X0021,0X14},//FS_CFG             FREQUENCY SYNTHESIZER CONFIGURATION
 {0X0026,0X00},//PKT_CFG2           PACKET CONFIGURATION REG. 2
 {0X0027,0X55},//PKT_CFG1           PACKET CONFIGURATION REG. 1
 {0X0028,0X20},//PKT_CFG0           PACKET CONFIGURATION REG. 0
 {0X002D,0X79},//PA_CFG0            POWER AMPLIFIER CONFIGURATION REG. 0
 {0X002E,0X18},//PKT_LEN            PACKET LENGTH CONFIGURATION
 {0X2F00,0X00},//IF_MIX_CFG         IF MIX CONFIGURATION
 {0X2F02,0X0A},//TOC_CFG            TIMING OFFSET CORRECTION CONFIGURATION
 {0X2F0C,0X6C},//FREQ2              FREQUENCY CONFIGURATION [23:16]
 {0X2F0D,0X80},//FREQ1              FREQUENCY CONFIGURATION [15:8]
 {0X2F12,0X00},//FS_DIG1            FREQUENCY SYNTHESIZER DIGITAL REG. 1
 {0X2F13,0X5F},//FS_DIG0            FREQUENCY SYNTHESIZER DIGITAL REG. 0
 {0X2F16,0X40},//FS_CAL1            FREQUENCY SYNTHESIZER CALIBRATION REG. 1
 {0X2F17,0X0E},//FS_CAL0            FREQUENCY SYNTHESIZER CALIBRATION REG. 0
 {0X2F19,0X03},//FS_DIVTWO          FREQUENCY SYNTHESIZER DIVIDE BY 2
 {0X2F1B,0X33},//FS_DSM0            FS DIGITAL SYNTHESIZER MODULE CONFIGURATION REG. 0
 {0X2F1D,0X17},//FS_DVC0            FREQUENCY SYNTHESIZER DIVIDER CHAIN CONFIGURATION ..
 {0X2F1F,0X50},//FS_PFD             FREQUENCY SYNTHESIZER PHASE FREQUENCY DETECTOR CON..
 {0X2F20,0X6E},//FS_PRE             FREQUENCY SYNTHESIZER PRESCALER CONFIGURATION
 {0X2F21,0X14},//FS_REG_DIV_CML     FREQUENCY SYNTHESIZER DIVIDER REGULATOR CONFIGURAT..
 {0X2F22,0XAC},//FS_SPARE           FREQUENCY SYNTHESIZER SPARE
 {0X2F27,0XB4},//FS_VCO0            FS VOLTAGE CONTROLLED OSCILLATOR CONFIGURATION REG..
 {0X2F32,0X0E},//XOSC5              CRYSTAL OSCILLATOR CONFIGURATION REG. 5
 {0X2F36,0X03},//XOSC1              CRYSTAL OSCILLATOR CONFIGURATION REG. 1
 {0XFFFF,0XFF}
};