环境:esp32+cc1101,spi接口,433MHz,38.4kbps, 2-FSK, fredev 50kHz
其它设置:包长可变,GDO0为IRQ,配置0x6,上升沿触发,Asserts when sync word has been sent/received, de-asserts at end of packet
遇到问题:
1)在发送函数中,先进入idle(确定已进入),装填TXFIFO,延时30us,再进入tx状态(也确定已进入),GDO0的中断即触发,在线程里处理该中断(下半文),每50us读取MARCSTATE的状态,显示为几个连续的tx状态,然后是连续的TXFIFO_UNDERFLOW, 如:19, 19, 19, 19, 19, 19, 22, 22, 22, 22, 22。。。十进制,即 idle->tx->txfifo_underflow。
从进入TX状态到触发冲断,log时间戳显示3ms左右,而从进入TX状态到TXFIFO_UNDERFLOW,时间戳显示总共7ms左右;在示波器上观察GDO0的高电平持续时间,大概6ms左右。
想问的问题是,如何判断tx发送已完成?正常的状态变化应该是19->20,而实际看到的是19->22,中断触发时表示发送已经完成,但读到的MARCSTATE状态却是tx,即19。
2)数据接收,数据长度常为0,或者一串乱码无法解析。问题,接收到的数据长度该如何获取?
3)用smart rf studio通过cc debuger连接 cc1101,作为一个独立的收发装置辅助调试。它接收不到esp32+cc1101发出来的包,尽管esp32+cc1101显示发送已完成并触发GDO0的中断;反过来它发出去的包,esp32+cc1101也接收不到。换言之,esp32+cc1101的发送和接收,尽管触发了GDO0的中断,实际上smart rf studio没有反应,当然确保了二者在参数配置上一致,如频率速率等。
已排除:spi通信没问题,寄存器能正确读写,burst也可以。
下面是我对寄存器的配置,也试过其它配置,基本差不多:
static const uint8_t preferredSettings433[39][2] =
{
{CC1101_REG_IOCFG2, 0x0D}, // High impedance (3-state)
{CC1101_REG_IOCFG1, 0x2E}, // Asserts when sync word has been sent/received, de-asserts at end of packet
{CC1101_REG_IOCFG0, 0x06}, // Asserts when sync word has been sent/received, de-asserts at end of packet
{CC1101_REG_FIFOTHR, 0x07}, // TX: 33 bytes; RX: 32 bytes
{CC1101_REG_SYNC1, 0xD3}, // Sync word high byte
{CC1101_REG_SYNC0, 0x91}, // Sync word low byte
{CC1101_REG_PKTLEN, 0x3D}, // Packet length 61 bytes
{CC1101_REG_PKTCTRL1, 0x04}, // No address check, append status, CRC autoflush
{CC1101_REG_PKTCTRL0, 0x45}, // Variable length packets, CRC enabled, whitening disabled
{CC1101_REG_ADDR, 0x00}, // Device address (disabled)
{CC1101_REG_CHANNR, 0x00}, // Channel number
{CC1101_REG_FSCTRL1, 0x06}, // Frequency synthesizer control
{CC1101_REG_FSCTRL0, 0x00}, // Frequency synthesizer control
{CC1101_REG_FREQ2, 0x10}, // Frequency: 433 MHz
{CC1101_REG_FREQ1, 0xA7}, // Frequency: 433 MHz
{CC1101_REG_FREQ0, 0x62}, // Frequency: 433 MHz
{CC1101_REG_MDMCFG4, 0xCA}, // Modem configuration
{CC1101_REG_MDMCFG3, 0x83}, // Modem configuration (38.4 kbps)
{CC1101_REG_MDMCFG2, 0x13}, // Modem configuration (2-FSK, no manchester, 16/16 sync word bits detected)
{CC1101_REG_MDMCFG1, 0x22}, // Modem configuration (FEC disabled, 4 preamble bytes)
{CC1101_REG_MDMCFG0, 0xF8}, // Modem configuration (Channel spacing exponent)
{CC1101_REG_DEVIATN, 0x50}, // Deviation setting (50 kHz)
{CC1101_REG_MCSM2, 0x07}, // Main Radio Control State Machine configuration
{CC1101_REG_MCSM1, 0x30}, // Main Radio Control State Machine configuration
{CC1101_REG_MCSM0, 0x18}, // Main Radio Control State Machine configuration
{CC1101_REG_FOCCFG, 0x16}, // Frequency Offset Compensation configuration
{CC1101_REG_BSCFG, 0x6C}, // Bit Synchronization configuration
{CC1101_REG_AGCCTRL2, 0x03}, // AGC control
{CC1101_REG_AGCCTRL1, 0x40}, // AGC control
{CC1101_REG_AGCCTRL0, 0x91}, // AGC control
{CC1101_REG_WOREVT1, 0x87}, // High byte Event 0 timeout
{CC1101_REG_WOREVT0, 0x6B}, // Low byte Event 0 timeout
{CC1101_REG_WORCTRL, 0xF8}, // Wake On Radio control
{CC1101_REG_FREND1, 0xB6}, // Front end RX configuration
{CC1101_REG_FREND0, 0x10}, // Front end RX configuration
{CC1101_REG_FSCAL3, 0xEA}, // Frequency synthesizer calibration
{CC1101_REG_FSCAL2, 0x0A}, // Frequency synthesizer calibration
{CC1101_REG_FSCAL1, 0x00}, // Frequency synthesizer calibration
{CC1101_REG_FSCAL0, 0x11}, // Frequency synthesizer calibration
};
期望进一步联系,mail: dunfa.chen@outlook.com