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cc3200 SPI 做master时,输出时钟有间隔

Other Parts Discussed in Thread: CC3200

各位大侠,

      我用cc3200 spi 做master使用dma输出时,发现时钟间有间隔,比如我设置dma为8bit ,发现每8个时钟脉冲之间有间隔,而不是连续的,请问这个正常吗,如何消除这个间隔。谢谢

    

  • 1680.7024.spi_demo_DMA.zip

    看看这个例子,或者你在本论坛搜索CC3200 SPI DMA关键字,能找到不少。

  • 我用ti sdk里面自带的spi的例程,非dma方式,发现也有这个问题。TI官方文档里有提到:t Lag— Minimum trailing time required for slave mode (guaranteed in master mode) after the last *** edge. 我说的 就是t Lag这个时间,没看明白guaranteed in master mode是什么意思,实测发现约有0.3us的,这个能改吗
  • 您可以看一下 给出的说明

    The SPI driver operates on some key definitions and assumptions:

    The driver operates transparent from the chip select. Some SPI controllers feature a hardware chip select to assert SPI slave peripherals. See the specific peripheral implementations on chip select requirements.

    The SPI protocol does not account for a built-in handshaking mechanism and neither does this SPI driver. Therefore, when operating in SPI_SLAVE mode, the application must provide such a mechanism to ensure that the SPI slave is ready for the SPI master. The SPI slave must call SPI_transfer() before the SPI master starts transmitting. Some example application mechanisms could include:

    Timed delays on the SPI master to guarantee the SPI slave is be ready for a SPI transaction.

    A form of GPIO flow control from the slave to the SPI master to notify the master when ready.

  • 关于SPI 连续发送时字节之间会有停顿问题,可以在初始化使用SPI_TURBO_ON 选项解决,我试验了一下在DMA模式下可行。查询模式下连续发送好像不行。