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1. 100K pull down resistor to GND should be provided to pins 34 and 35
2. Pull up to VBAT option with 69.8k resistor should be provided at SOP0 (pin #35). This is required if user chooses to use SWD debug mode instead of 4 wire JTAG
3. 10K pull down resistor to GND should be provided to pin 21
4. Pull up to VBAT option with 69.8k resistor should be provided at SOP2 (pin #21). This is required for entering the UART load mode for flashing FW, application, certificate etc. 5. Please place a .6 pF cap close to the pin.
Note : The SOP0 and SOP1 lines would be driven low by the device in hibernate state. This can lead to higher leakage in case a pull-up resistor is added on this line. Hence it is recommended to keep pull-down on these pins on final product. For SWD mode, the line can be pulled high by emulator/debugger.
