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你说的是GDO 0吧？
Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial mode. When using this mode, sync
detection should be disabled together with CRC calculation ( MDMCFG2.SYNC_MODE=000 and
PKTCTRL0.CRC_EN=0). Infinite packet length mode should be used (
PKTCTRL0.LENGTH_CONFIG=10b).
In synchronous serial mode, data is transferred on a two-wire serial interface. The CC110L provides a
clock that is used to set up new data on the data input line or sample data on the data output line. Data
input (TX data) is on the GDO0 pin. This pin will automatically be configured as an input when TX is
active. The TX latency is 8 bits. The data output pin can be any of the GDO pins. This is set by the
IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG fields. The RX latency is 9 bits.
The MCU must handle preamble and sync word detection in software.
The MCU must handle preamble and sync word insertion/detection in software, together with CRC
calculation and insertion.
你设置为06 代表
Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will also de-assert
when a packet is discarded due to address or maximum length filtering or when the radio enters RXFIFO_OVERFLOW state.
In TX the pin will de-assert if the TX FIFO underflows.
