cc1352P芯片读取A/D芯片ads131a04

在C:\ti\simplelink_cc13x2_26x2_sdk_3_20_00_68\source\ti\drivers\spi\里面的SPICC26X2DMA 
*  ======== *** ========
 */
static void ***(uintptr_t arg0, uintptr_t arg1) {
    SPI_Transaction     *transaction;
    *** *object = ((SPI_Handle) arg0)->object;

    while (object->completedTransfers != NULL) {
        transaction = object->completedTransfers;

        /* Move object->completedTransfers to the next transaction */
        object->completedTransfers = object->completedTransfers->nextPtr;

        transaction->nextPtr = NULL;

        /* Transaction complete; release power constraints */
        releaseConstraint((uint32_t) transaction->txBuf);

        /* Execute callback function for completed transfer */
        object->transferCallbackFxn((SPI_Handle) arg0, transaction);
    }
}

/*
 *  ======== *** ========
 */
bool ***(SPI_Handle handle, SPI_Transaction *transaction)
{
    uint8_t                       alignMask;
    bool                          buffersAligned;
    uintptr_t                     key;
    ***          *object = handle->object;
    *** const *hwAttrs = handle->hwAttrs;

    if (transaction->count == 0) {
        return (false);
    }

    key = HwiP_disable();

    /*
     * Make sure that the buffers are aligned properly.
     * alignMask is used to check if the RX/TX buffers addresses
     * are aligned to the frameSize.
     */
    alignMask = (object->dataSize < 9) ? 0x0 : 0x01;
    buffersAligned = ((((uint32_t) transaction->rxBuf & alignMask) == 0) &&
                     (((uint32_t) transaction->txBuf & alignMask) == 0));

    if (!buffersAligned ||
        (object->headPtr && object->transferMode == SPI_MODE_BLOCKING)) {
        transaction->status = SPI_TRANSFER_FAILED;

        HwiP_restore(key);

        return (false);
    }
    else {
        if (object->headPtr) {
            object->tailPtr->nextPtr = transaction;
            object->tailPtr = transaction;
            object->tailPtr->status = SPI_TRANSFER_QUEUED;
        }
        else {
            object->headPtr = transaction;
            object->tailPtr = transaction;

            object->framesQueued = 0;
            object->framesTransferred = 0;
            object->priTransferSize = 0;
            object->altTransferSize = 0;
            object->tailPtr->status =
                    (object->returnPartial != ***) ?
                     SPI_TRANSFER_PEND_CSN_ASSERT :
                     SPI_TRANSFER_STARTED;
        }

        object->tailPtr->nextPtr = NULL;
    }

    /* In slave mode, optionally enable callback on CSN de-assert */
    if (object->returnPartial == ***) {
        object->returnPartial = ***;
        PIN_setInterrupt(object->pinHandle, object->csnPin | PIN_IRQ_BOTHEDGES);
    }

    /* Set constraints to guarantee transaction */
    setConstraint((uint32_t)transaction->txBuf);

    /*
     * Polling transfer if BLOCKING mode & transaction->count < threshold
     * Slaves not allowed to use polling unless timeout is disabled
     */
    if (object->transferMode == SPI_MODE_BLOCKING &&
        transaction->count < hwAttrs->minDmaTransferSize &&
        (object->mode == SPI_MASTER ||
        object->transferTimeout == SPI_WAIT_FOREVER)) {
        HwiP_restore(key);

        spiPollingTransfer(object, hwAttrs, transaction);

        /* Release constraint since transaction is done */
        releaseConstraint((uint32_t) transaction->txBuf);

        /* Transaction completed; set status & mark SPI ready */
        object->headPtr->status = SPI_TRANSFER_COMPLETED;
        object->headPtr = NULL;
        object->tailPtr = NULL;
    }
    else {
        /*
         * Perform a DMA backed SPI transfer; we need exclusive access while
         * priming the transfer to prevent race conditions with
         * ***().
         */
        primeTransfer(object, hwAttrs);