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TLV320AIC3204EVM-K: TLV320AIC3204EVM-K The initialization configuration cannot take effect

Part Number: TLV320AIC3204EVM-K
Other Parts Discussed in Thread: TLV320AIC3204

TI_PAGE_0_REGISTERS.xls Code_register_initialization_function.txt 

HI,

I have reviewed the TLV320AIC3204 datasheet and the application notes, but still have the following doubts :

**Problem A: Initialization configuration does not take effect**

When I use the "High Performance Stereo Playback" preset in the Windows GUI Tool (TLV320AIC3204 CS) to send the configuration via the USB-to-I2C adapter, the module plays audio using tinyplay, and the headphone output produces sound normally (J7 headphone channel).

However, when I port this set of register configurations to the `codec_probe` initialization function in the Linux driver (writing the same register values via I2C), the configuration does not take effect, and there is no sound from the headphones. At this point, the sound is only restored after re-sending the configuration once more using the Windows tool.

Below are the register parameters when the headphones are playing normally, exported from the tool:
`TI_PAGE_0_REGISTERS.xls`

This functional documentation is used to set the default loaded register values in the TLV3204 via I2C, but it does not work during current testing.
`Code_register_initialization_function.txt`

I have added the corresponding document to the attachment

 

**Problem B: No sound on the speaker path (J6 speaker)**

Under the premise that the headphone path is working normally (as described above), the speaker path consistently produces no sound output. We have already confirmed that the I2S audio data sent from the module to the TLV320AIC3204 is normal (verified via oscilloscope/other methods).

 

Any guidance would be greatly appreciated.

Best regards,

Hank

  • Can you re-attach TI_PAGE_0_REGISTERS.xls? I do not see the attachment here. 

    With both of these issues, can you send a register dump of when you are trying to playback? Both when it doesn't work and when it does. This will be the most helpful. Most likely, the Linux drivers are changing the registers when you run tinyplay, after initialization. You are using this driver, correct? https://www.ti.com/tool/TLV320AIC32X4SW-LINUX

    Can you send a schematic as well? Or are you just using the EVM?

  • Hi

    I didn't use the driver in this. "">www.ti.com/.../TLV320AIC32X4SW-LINUX"

    The attachment is a register table exported using the tlv3204_cs tool when it can be played normally. At this time, the TLVAIC3204_54_RHB_EVM board has sound from J7 LINE OUT, but not from J6

    1588.TI_PAGE_0_REGISTERS.xls

  • Hi

    I didn't use the driver in this. "">www.ti.com/.../TLV320AIC32X4SW-LINUX"

    The attachment is a register table exported using the tlv3204_cs tool when it can be played normally. At this time, the TLVAIC3204_54_RHB_EVM board has sound from J7 LINE OUT, but not from J6

    7142.TI_PAGE_0_REGISTERS.xls

  • Hi

    I didn't use the driver in this. "">www.ti.com/.../TLV320AIC32X4SW-LINUX"

    The attachment is a register table exported using the tlv3204_cs tool when it can be played normally. At this time, the TLVAIC3204_54_RHB_EVM board has sound from J7 LINE OUT, but not from J6

    i2caddr_0x52_register_init.txt: This document contains the initialization function to be executed during the probe of the snd_soc_component_driver. The i2caddr is set to 0x52, and the register parameters exported by the tlv3204_cs tool are referenced. As long as the project board is powered on, this initialization must be executed. Then, audio is played through tinyplay. However, it is ineffective in actual testing. Sound output can only be achieved through the load item in the playback section of the tlv3204_cs tool

    5554.TI_PAGE_0_REGISTERS.xls

    void tlv320aic3x_register_init(void)
    {
    tlv320aic3x_write(0x00, 0x00);
    tlv320aic3x_write(0x01, 0x00);
    tlv320aic3x_write(0x02, 0x60);
    tlv320aic3x_write(0x03, 0x00);
    tlv320aic3x_write(0x04, 0x00);
    tlv320aic3x_write(0x05, 0x11);
    tlv320aic3x_write(0x06, 0x04);
    tlv320aic3x_write(0x07, 0x00);
    tlv320aic3x_write(0x08, 0x00);
    tlv320aic3x_write(0x09, 0x00);
    tlv320aic3x_write(0x0A, 0x00);
    tlv320aic3x_write(0x0B, 0x81);
    tlv320aic3x_write(0x0C, 0x84);
    tlv320aic3x_write(0x0D, 0x00);
    tlv320aic3x_write(0x0E, 0x40);
    tlv320aic3x_write(0x0F, 0x02);
    tlv320aic3x_write(0x10, 0x00);
    tlv320aic3x_write(0x11, 0x08);
    tlv320aic3x_write(0x12, 0x01);
    tlv320aic3x_write(0x13, 0x01);
    tlv320aic3x_write(0x14, 0x80);
    tlv320aic3x_write(0x15, 0x01);
    tlv320aic3x_write(0x16, 0x00);
    tlv320aic3x_write(0x17, 0x04);
    tlv320aic3x_write(0x18, 0x00);
    tlv320aic3x_write(0x19, 0x00);
    tlv320aic3x_write(0x1A, 0x01);
    tlv320aic3x_write(0x1B, 0x00);
    tlv320aic3x_write(0x1C, 0x00);
    tlv320aic3x_write(0x1D, 0x00);
    tlv320aic3x_write(0x1E, 0x01);
    tlv320aic3x_write(0x1F, 0x00);
    tlv320aic3x_write(0x20, 0x00);
    tlv320aic3x_write(0x21, 0x00);
    tlv320aic3x_write(0x22, 0x00);
    tlv320aic3x_write(0x23, 0x00);
    tlv320aic3x_write(0x24, 0x00);
    tlv320aic3x_write(0x25, 0xEE);
    tlv320aic3x_write(0x26, 0x11);
    tlv320aic3x_write(0x27, 0x00);
    tlv320aic3x_write(0x28, 0x00);
    tlv320aic3x_write(0x29, 0x00);
    tlv320aic3x_write(0x2A, 0xE0);
    tlv320aic3x_write(0x2B, 0x00);
    tlv320aic3x_write(0x2C, 0x0C);
    tlv320aic3x_write(0x2D, 0x00);
    tlv320aic3x_write(0x2E, 0x00);
    tlv320aic3x_write(0x2F, 0x00);
    tlv320aic3x_write(0x30, 0x00);
    tlv320aic3x_write(0x31, 0x00);
    tlv320aic3x_write(0x32, 0x00);
    tlv320aic3x_write(0x33, 0x00);
    tlv320aic3x_write(0x34, 0x00);
    tlv320aic3x_write(0x35, 0x12);
    tlv320aic3x_write(0x36, 0x03);
    tlv320aic3x_write(0x37, 0x02);
    tlv320aic3x_write(0x38, 0x02);
    tlv320aic3x_write(0x39, 0x00);
    tlv320aic3x_write(0x3A, 0x00);
    tlv320aic3x_write(0x3B, 0x00);
    tlv320aic3x_write(0x3C, 0x08);
    tlv320aic3x_write(0x3D, 0x01);
    tlv320aic3x_write(0x3E, 0x00);
    tlv320aic3x_write(0x3F, 0xD6);
    tlv320aic3x_write(0x40, 0x00);
    tlv320aic3x_write(0x41, 0x00);
    tlv320aic3x_write(0x42, 0x00);
    tlv320aic3x_write(0x43, 0x00);
    tlv320aic3x_write(0x44, 0x6F);
    tlv320aic3x_write(0x45, 0x38);
    tlv320aic3x_write(0x46, 0x00);
    tlv320aic3x_write(0x47, 0x00);
    tlv320aic3x_write(0x48, 0x00);
    tlv320aic3x_write(0x49, 0x00);
    tlv320aic3x_write(0x4A, 0x00);
    tlv320aic3x_write(0x4B, 0xEE);
    tlv320aic3x_write(0x4C, 0x10);
    tlv320aic3x_write(0x4D, 0xD8);
    tlv320aic3x_write(0x4E, 0x7E);
    tlv320aic3x_write(0x4F, 0xE3);
    tlv320aic3x_write(0x50, 0x00);
    tlv320aic3x_write(0x51, 0x00);
    tlv320aic3x_write(0x52, 0x88);
    tlv320aic3x_write(0x53, 0x00);
    tlv320aic3x_write(0x54, 0x00);
    tlv320aic3x_write(0x55, 0x00);
    tlv320aic3x_write(0x56, 0x00);
    tlv320aic3x_write(0x57, 0x00);
    tlv320aic3x_write(0x58, 0x7F);
    tlv320aic3x_write(0x59, 0x00);
    tlv320aic3x_write(0x5A, 0x00);
    tlv320aic3x_write(0x5B, 0x00);
    tlv320aic3x_write(0x5C, 0x00);
    tlv320aic3x_write(0x5D, 0x00);
    tlv320aic3x_write(0x5E, 0x00);
    tlv320aic3x_write(0x5F, 0x00);
    tlv320aic3x_write(0x60, 0x7F);
    tlv320aic3x_write(0x61, 0x00);
    tlv320aic3x_write(0x62, 0x00);
    tlv320aic3x_write(0x63, 0x00);
    tlv320aic3x_write(0x64, 0x00);
    tlv320aic3x_write(0x65, 0x00);
    tlv320aic3x_write(0x66, 0x00);
    tlv320aic3x_write(0x67, 0x00);
    tlv320aic3x_write(0x68, 0x00);
    tlv320aic3x_write(0x69, 0x00);
    tlv320aic3x_write(0x6A, 0x00);
    tlv320aic3x_write(0x6B, 0x00);
    tlv320aic3x_write(0x6C, 0x00);
    tlv320aic3x_write(0x6D, 0x00);
    tlv320aic3x_write(0x6E, 0x00);
    tlv320aic3x_write(0x6F, 0x00);
    tlv320aic3x_write(0x70, 0x00);
    tlv320aic3x_write(0x71, 0x00);
    tlv320aic3x_write(0x72, 0x00);
    tlv320aic3x_write(0x73, 0x00);
    tlv320aic3x_write(0x74, 0x00);
    tlv320aic3x_write(0x75, 0x00);
    tlv320aic3x_write(0x76, 0x00);
    tlv320aic3x_write(0x77, 0x00);
    tlv320aic3x_write(0x78, 0x00);
    tlv320aic3x_write(0x79, 0x00);
    tlv320aic3x_write(0x7A, 0x00);
    tlv320aic3x_write(0x7B, 0x00);
    tlv320aic3x_write(0x7C, 0x00);
    tlv320aic3x_write(0x7D, 0x00);
    tlv320aic3x_write(0x7E, 0x00);
    tlv320aic3x_write(0x7F, 0x00);
    
    
    
    }
    

  • There are some differences between your Code_register_initialization_function.txt and TI_PAGE_0_REGISTERS.xls. First and most obvious, in the xls there is just page 0. However to fully initialize the device you will need to write to some page 1 registers. You included a page 1 section in the .txt file, are you writing those registers as well?

       // ========== Step 5: Switch to Page1 for Analog Section Configuration ==========
        tlv320aic3x_write(0x00, 0x01);    // Page 1
    
        // Power configuration
        tlv320aic3x_write(0x01, 0x08);    // Disable coarse AVDD generation
        tlv320aic3x_write(0x02, 0x00);    // Main analog power control enable
        tlv320aic3x_write(0x7B, 0x01);    // REF charging time 40ms
        msleep(50);                     // Wait for REF to stabilize
    
        // Soft stepping configuration (to reduce pop noise)
        tlv320aic3x_write(0x14, 0x25);    // HP soft stepping setting
        tlv320aic3x_write(0x15, 0x25);    // Same as above
    
        // Common mode voltage
        tlv320aic3x_write(0x0A, 0x00);    // 0.9V
    
        // ========== Step 6: Configure Output Routing ==========
        // Configure routing for HPL/HPR (J7) and LOL/LOR (J6) simultaneously
        tlv320aic3x_write(0x0C, 0x08);    // Left DAC -> HPL
        tlv320aic3x_write(0x0D, 0x08);    // Right DAC -> HPR 
        tlv320aic3x_write(0x0E, 0x08);    // Left DAC -> LOL 
        tlv320aic3x_write(0x0F, 0x08);    // Right DAC -> LOR
    
        // Output gain (0dB)
        tlv320aic3x_write(0x10, 0x00);    // HPL gain
        tlv320aic3x_write(0x11, 0x00);    // HPR gain
        tlv320aic3x_write(0x12, 0x00);    // LOL gain
        tlv320aic3x_write(0x13, 0x00);    // LOR gain
    
        // ========== Step 7: Power Up Output Drivers ==========
        tlv320aic3x_write(0x09, 0x3C);    // Power up HPL, HPR, LOL, LOR simultaneously
    
        // ========== Step 8: Wait for Soft Stepping to Complete ==========
        // Method 1: Fixed delay (simple)
        msleep(2500);                   // Soft stepping takes 2.5 seconds (adjust based on coupling capacitor)

  • Hi ,

    All register initializations are done in the txt file function. An if condition is used to distinguish between the two options. No other registers are set

  • Hi,

    All register initializations are done in the txt file function. An if condition is used to distinguish between the two options. No other registers are set

  • If there are not writes to page 1, then there will be no routing to the headphones and there will not be sound output from the DAC. Please make sure your register writes include all registers in the default playback script. 

    Here is the default script from the GUI for future reference:

    ###############################################
    # High Performance Stereo Playback
    # ---------------------------------------------
    # PowerTune mode PTM_P3 is used for high
    # performance 16-bit audio. For PTM_P4,
    # an external audio interface that provides
    # 20-bit audio is required.
    #
    # For normal USB Audio, no hardware change
    # is required.
    #
    # If using an external interface, SW2.4 and
    # SW2.5 of the USB-ModEVM must be set to
    # HI and clocks can be connected to J14 of
    # the USB-ModEVM.
    #
    # Audio is routed to both headphone and
    # line outputs.
    ###############################################
    
    
    
    ###############################################
    # Software Reset
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # Initialize the device through software reset
    w 30 01 01
    #
    ###############################################
    
    
    
    ###############################################
    # Clock Settings
    # ---------------------------------------------
    # The codec receives: MCLK = 11.2896 MHz,
    # BLCK = 2.8224 MHz, WCLK = 44.1 kHz
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # NDAC = 1, MDAC = 2
    w 30 0b 81 82
    #
    ###############################################
    
    
    
    ###############################################
    # Signal Processing Settings
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # Set the DAC Mode to PRB_P8
    w 30 3c 08
    #
    ###############################################
    
    
    
    ###############################################
    # Initialize Codec
    ###############################################
    #
    # Select Page 1
    w 30 00 01
    #
    # Disable weak AVDD in presence of external
    # AVDD supply
    w 30 01 08
    #
    # Enable Master Analog Power Control
    w 30 02 00
    #
    # Set the input powerup time to 3.1ms (for ADC)
    # w 30 47 32
    #
    # Set the REF charging time to 40ms
    w 30 7b 01
    #
    ###############################################
    
    
    
    ###############################################
    # Playback Setup
    ###############################################
    #
    # Select Page 1
    w 30 00 01
    #
    # De-pop
    w 30 14 25
    #
    # Route LDAC/RDAC to HPL/HPR
    w 30 0c 08 08
    #
    # Route LDAC/RDAC to LOL/LOR
    w 30 0e 08 08
    #
    # Power up HPL/HPR and LOL/LOR drivers
    w 30 09 3C
    #
    # Unmute HPL/HPR driver, 0dB Gain
    w 30 10 00 00
    #
    # Unmute LOL/LOR driver, 0dB Gain
    w 30 12 00 00
    #
    # Select Page 0
    w 30 00 00
    #
    # DAC => 0dB
    w 30 41 00 00
    #
    # Power up LDAC/RDAC
    w 30 3f d6
    #
    # Unmute LDAC/RDAC
    w 30 40 00
    #
    ###############################################
  • After trying this recommended procedure, the register configuration still did not take effect. Based on our conditional checks, we will write to register page 1. There may still be discrepancies from the recommended process in other areas. I would like to know if you could share the complete register configuration procedure. And we can check the differences

    Thank you very much

  • I had no issues using just that default script to configure the device. It contains a software reset at the beginning, writing 0x01 to register 1 in page 0 which will reset all registers to the default. So, only the registers written in the script after the software reset are the registers that you will need to set. I would recommend doing a software reset before your script start as well.