mclk为12.288MHz，
用adb执行如下命令播放48K_16bit_stereo.wav时，寄存器配置如下log：
tinymix "QUAT_MI2S_RX Audio Mixer MultiMedia1" "1"
tinymix "HPL Output Mixer L_DAC Switch" "1"
tinymix "HP DAC Playback Switch" "1"
tinyplay /sdcard/48K_16bit_stereo.wav
log：
[aic32x4] aic32x4_write page = 1, reg = c(012), val = 8 //Left Channel DAC reconstruction filter's positive terminal is routed to HPL
[aic32x4] aic32x4_write page = 1, reg = 10(016), val = 0 //HPL driver gain is 0dB
[aic32x4] aic32x4_write page = 1, reg = 11(017), val = 0 //HPR driver gain is 0dB
[aic32x4] aic32x4_write page = 0, reg = 40(064), val = 12 //Left DAC Channel muted,Right DAC Channel muted
[aic32x4] aic32x4_write page = 0, reg = 4(004), val = 3 //PLL Clock is CODEC_CLKIN
[aic32x4] aic32x4_write page = 0, reg = 1d(029), val = 1 //BDIV_CLKIN = DAC_MOD_CLK
[aic32x4] aic32x4_write page = 0, reg = 5(005), val = 17 //PLL divider P Value 1,PLL divider R Value 1
[aic32x4] aic32x4_write page = 0, reg = 6(006), val = 8 //PLL divider J value 8
[aic32x4] aic32x4_write page = 0, reg = 7(007), val = 7 //PLL divider D value (MSB) 7
[aic32x4] aic32x4_write page = 0, reg = 8(008), val = 128 //PLL divider D value (LSB) 128
[aic32x4] aic32x4_write page = 0, reg = b(011), val = 2 //NDAC Value 2
[aic32x4] aic32x4_write page = 0, reg = c(012), val = 8 //MDAC Value 8
[aic32x4] aic32x4_write page = 0, reg = d(013), val = 0 //DAC OSR (DOSR) Setting MSB
[aic32x4] aic32x4_write page = 0, reg = e(014), val = 128 //DAC OSR (DOSR) Setting LSB 128
[aic32x4] aic32x4_write page = 0, reg = 12(018), val = 2 //NADC Value 2
[aic32x4] aic32x4_write page = 0, reg = 13(019), val = 8 //MADC Value 8
[aic32x4] aic32x4_write page = 0, reg = 14(020), val = 128 //128(Use with PRB_R1 to PRB_R6, ADC Filter Type A)
[aic32x4] aic32x4_write page = 0, reg = 1e(030), val = 4 //BCLK N Divider value 4
[aic32x4] aic32x4_write page = 0, reg = 1b(027), val = 0 //Audio Interface = I2S Data Word length = 16 bits BCLK is input to the device WCLK is input to the
[aic32x4] aic32x4_write page = 0, reg = 3f(063), val = 148 //Left DAC Channel Powered Up,Left DAC data Left Channel Audio Interface Data,Soft-Stepping is 1
[aic32x4] aic32x4_write page = 1, reg = 9(009), val = 32 //HPL is powered up
[aic32x4] aic32x4_write page = 0, reg = 5(005), val = 145 //PLL is powered up,PLL divider P Value 1,PLL divider R Value 1
[aic32x4] aic32x4_write page = 0, reg = b(011), val = 130 //NDAC divider powered up,NDAC Value 2
[aic32x4] aic32x4_write page = 0, reg = c(012), val = 136 //MDAC divider powered up,MDAC Value 8
[aic32x4] aic32x4_write page = 0, reg = 12(018), val = 130 //NADC divider powered up,NADC Value 2
[aic32x4] aic32x4_write page = 0, reg = 13(019), val = 136 //MADC divider powered up,MADC Value 8
[aic32x4] aic32x4_write page = 0, reg = 1e(030), val = 132 //BCLK N divider powered up,BCLK N Divider value 4
[aic32x4] aic32x4_write page = 0, reg = 40(064), val = 0 //Left and Right Channel have independent volume control, not muted
