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您好,
1K电阻时是不能拉至0.8V以下是吗?如果是这样的话,那应该是FAULTZ pin内部晶体管导通电阻太大的缘故。FAULTZ pin是OD输出,内部晶体管导通时输出低电平,如果其导通电阻太大,与外接的上拉电阻分压就会偏高,使得其输出低电平不满足SDZ pin输入规格: