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TLV320ADC5120: 使用I2C配置后，BCLK和FSYNC有波形，SDOUT无输出，DEV_STS状态寄存器指示ADC channel power down

?? ?
Prodigy 10 points
Part Number: TLV320ADC5120

input采用2通道模拟差分输入，用I2c配置5120，BCLK和FSYNC有波形，SDOUT无输出。然后我查看DEV_STS状态寄存器发现值是c0（active mode， adc ch power down状态），但我设置了IN_CH_EN其中的ch1和ch2为enable状态。

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i2c_write(PAGE_CFG_ADDRESS, PAGE_CFG_PAGE_0);
i2c_write(SW_RESET_ADDRESS, SW_RESET_RESET);
bflb_mtimer_delay_ms(10);
i2c_write(SLEEP_CFG_ADDRESS, SLEEP_CFG_AREG_SELECT_INTERNAL | SLEEP_CFG_SLEEP_ENZ_ACTIVE);
bflb_mtimer_delay_ms(10);
i2c_write(ASI_CFG0_ADDRESS, ASI_CFG0_FORMAT_LJ | ASI_CFG0_WLEN_32_BITS);
i2c_write(ASI_CH1_ADDRESS, ASI_CH1_CH1_SLOT_0);
i2c_write(ASI_CH2_ADDRESS, ASI_CH2_CH2_SLOT_32);
i2c_write(MST_CFG0_ADDRESS, MST_CFG0_MST_SLV_CFG_MASTER | MST_CFG0_FS_MODE_48_KHZ | MST_CFG0_MCLK_FREQ_SEL_12_MHZ);//mclk = 256 * freq_sample
i2c_write(MST_CFG1_ADDRESS, MST_CFG1_FS_RATE_44P1_48_KHZ | MST_CFG1_FS_BCLK_RATIO_64);
i2c_write(CLK_SRC_ADDRESS, CLK_SRC_DIS_PLL_SLV_CLK_SRC_BCLK | CLK_SRC_MCLK_FREQ_SEL_MODE_MCLK_FREQ_SEL | CLK_SRC_MCLK_RATIO_SEL_256);//ratio = clk / FSYNC
i2c_write(GPIO_CFG0_ADDRESS, GPIO_CFG0_GPIO1_CFG_IRQ | GPIO_CFG0_GPIO1_DRV_ACTLOW_WEAKHIGH);
i2c_write(GPO_CFG0_ADDRESS, GPO_CFG0_GPO1_CFG_DISABLED);
i2c_write(GPI_CFG0_ADDRESS, GPI_CFG0_GPI1_CFG_DISABLED | GPI_CFG0_GPI2_CFG_DISABLED);
i2c_write(INT_MASK0_ADDRESS, ~INT_MASK0_VAD_POWERUP_MASK);
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

询问如何才能power up以及SDO输出数据。

  • 0
    Prodigy 10 points

    附上原理图

  • 0
    TI__Guru**** 185470 points

    您好，

    DEV_STS0寄存器值是C0的话，是使能了ch1和ch2：

    FSYNC和BCLK实际测量频率是多少？波形质量怎样？设置的采样率是多少？

    您是否验证了寄存器写入后可以正确读出来？您可以读出您的寄存器配置吗？

    I2C上的对地电容去掉。

  • 0 回复 Amy Luo
    Prodigy 10 points

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    {PAGE_CFG_ADDRESS, PAGE_CFG_PAGE_0},
    {SW_RESET_ADDRESS, SW_RESET_RESET},
    {SLEEP_CFG_ADDRESS, SLEEP_CFG_AREG_SELECT_INTERNAL | SLEEP_CFG_SLEEP_ENZ_ACTIVE},
    {ASI_CFG0_ADDRESS, ASI_CFG0_FORMAT_LJ | ASI_CFG0_WLEN_32_BITS},
    {ASI_CH1_ADDRESS, ASI_CH1_CH1_SLOT_0},
    {ASI_CH2_ADDRESS, ASI_CH2_CH2_SLOT_32},
    {MST_CFG0_ADDRESS, MST_CFG0_MST_SLV_CFG_MASTER | MST_CFG0_AUTO_CLK_CFG_ENABLED | MST_CFG0_AUTO_MODE_PLL_DIS_ENABLED | MST_CFG0_BCLK_FSYNC_GATE_NO_GATING | MST_CFG0_FS_MODE_48_KHZ | MST_CFG0_MCLK_FREQ_S
    EL_12P288_MHZ},//mclk = 256 * freq_sample
    {MST_CFG1_ADDRESS, MST_CFG1_FS_RATE_44P1_48_KHZ | MST_CFG1_FS_BCLK_RATIO_64},
    {CLK_SRC_ADDRESS, CLK_SRC_DIS_PLL_SLV_CLK_SRC_BCLK | CLK_SRC_MCLK_FREQ_SEL_MODE_MCLK_FREQ_SEL | CLK_SRC_MCLK_RATIO_SEL_256},//ratio = clk / FSYNC
    {GPIO_CFG0_ADDRESS, GPIO_CFG0_GPIO1_CFG_IRQ | GPIO_CFG0_GPIO1_DRV_ACTLOW_WEAKHIGH},
    {GPO_CFG0_ADDRESS, GPO_CFG0_GPO1_CFG_DISABLED},
    {GPI_CFG0_ADDRESS, GPI_CFG0_GPI1_CFG_DISABLED | GPI_CFG0_GPI2_CFG_DISABLED},
    {INT_MASK0_ADDRESS, ~INT_MASK0_VAD_POWERUP_MASK},
    {CM_TOL_CFG_ADDRESS, CM_TOL_CFG_CH1_INP_100mVpp | CM_TOL_CFG_CH2_INP_100mVpp},
    {BIAS_CFG_ADDRESS, BIAS_CFG_MBIAS_VAL_VREF | BIAS_CFG_ADC_FSCALE_1VRMS},
    {CH1_CFG0_ADDRESS, CH1_CFG0_INTYP_MIC | CH1_CFG0_INSRC_DIFF | CH1_CFG0_DC_AC | CH1_CFG0_IMP_2P5k | CH1_CFG0_DREEN_DISABLED},
    {CH1_CFG1_ADDRESS, CH1_CFG1_GAIN_42dB},
    {CH1_CFG2_ADDRESS, CH1_CFG2_DVOL_27dB},
    {CH2_CFG0_ADDRESS, CH2_CFG0_INTYP_MIC | CH2_CFG0_INSRC_DIFF | CH2_CFG0_DC_AC | CH2_CFG0_IMP_2P5k | CH2_CFG0_DREEN_DISABLED},
    {CH2_CFG1_ADDRESS, CH2_CFG1_GAIN_42dB},
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    1. 我打印了DEV_STS1的值是0xc0

    2. Fsync和Bclk的实际测量的值和我设想的差很远，我本意是Fsync=48k,Mclk=256xFsync=12.288m,Bclk=Fsync * 32bit * 2channel =3072000

    3.我读取ASI_STS的值是0x14

    4. 我验证了写入I2c后读取验证成功

    附上I2c设置的值

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    [10:31:45.142] - ·[0m[I][5120] address:00 value:00(00)
    [10:31:45.146] - ·[0m[I][5120] address:01 value:00(01)
    [10:31:45.147] - ·[0m[I][5120] address:02 value:81(81)
    [10:31:45.157] - ·[0m[I][5120] address:07 value:b0(b0)
    [10:31:45.166] - ·[0m[I][5120] address:0b value:00(00)
    [10:31:45.177] - ·[0m[I][5120] address:0c value:20(20)
    [10:31:45.189] - ·[0m[I][5120] address:13 value:81(81)
    [10:31:45.198] - ·[0m[I][5120] address:14 value:42(42)
    [10:31:45.207] - ·[0m[I][5120] address:16 value:88(88)
    [10:31:45.217] - ·[0m[I][5120] address:21 value:22(22)
    [10:31:45.227] - ·[0m[I][5120] address:22 value:00(00)
    [10:31:45.237] - ·[0m[I][5120] address:2b value:00(00)
    [10:31:45.247] - ·[0m[I][5120] address:33 value:ef(ef)
    [10:31:45.257] - ·[0m[I][5120] address:3a value:00(00)
    [10:31:45.267] - ·[0m[I][5120] address:3b value:02(02)
    [10:31:45.277] - ·[0m[I][5120] address:3c value:00(00)
    [10:31:45.287] - ·[0m[I][5120] address:3d value:a8(a8)
    [10:31:45.297] - ·[0m[I][5120] address:3e value:ff(ff)
    [10:31:45.306] - ·[0m[I][5120] address:41 value:00(00)
    [10:31:45.317] - ·[0m[I][5120] address:42 value:a8(a8)
    [10:31:45.327] - ·[0m[I][5120] address:43 value:ff(ff)
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0
    Prodigy 10 points

    我配置成SLAVE模式，BCLK和FSYNC由单片机这边产生就没有问题，但是配置成master模式，产生的时钟（BCLK和FSYNC）就是错的。该如何设置产生正确的时钟？

  • 0 回复 ?? ?
    TI__Guru**** 185470 points

    配置成master模式时，您需要输入MCLK，您是使用哪个管脚输入的MCLK时钟？GPI还是GPIO，寄存器没看出来您配置。

    下面应用手册有将TLV320ADCx120 配置为音频总线master 时所需的输入参数和寄存器系数，您看下对您寄存器配置有帮助：

    https://www.ti.com/lit/an/sbaa495a/sbaa495a.pdf

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