Input LVDS clock is standard clock as follows.
However the output LVDS clock (pin12/13) is deformed, see unwanted signal in red circle in below picture. Output pin12/13 is terminated with 100-ohm resistor close to LKM1D1212.
What's going wrong?
Input LVDS clock is standard clock as follows.
However the output LVDS clock (pin12/13) is deformed, see unwanted signal in red circle in below picture. Output pin12/13 is terminated with 100-ohm resistor close to LKM1D1212.
What's going wrong?
