LMX2594: 2594回读寄存器值不正确

Part Number: LMX2594

在配置2594全辅助校准模式下,读回读寄存器完全不正确,R110,R111,R112以及专用的回读寄存器R107,R108,R109也不正确,但是读我写入的寄存器是正确无误的;R0为2418,有什么地方是需要配置的吗

  • 您好

    您使用过评估板和TICS Pro进行配置吗

  • 按照tics pro配置寄存器表的,已实现半辅助模式,现在在全辅助模式下回读不正确,第一个点就回读不正确

  • 按照tics pro配置的寄存器表,已经实现半辅助校准模式,在全辅助下回读不正确,第一个频点不正确,且用频谱仪观察频率表示已锁定

  • 方便把您的配置发给我们看一下吗

  • 请问有收到我发的代码吗


  • module lmx2594_config(
    input clk_in ,
    input rst_n ,
    input ini_en ,
    input lowfreq_on ,
    input [5:0] out_pwr ,
    input wire [31:0] freq_target ,
    input wire freq_target_en ,
    input freq_vco_scan_en ,
    input pll_en ,
    input [18:0] pll_n ,
    input [31:0] pll_num ,
    input [2:0] vco_sel ,
    input [8:0] vco_daciset_strt ,
    input [7:0] vco_capctrl_strt ,
    input vco_param_en ,
    input [5:0] chdiv ,
    input seg1_en ,
    input [1:0] outa_mux ,
    output reg [2:0] MASH_ORDER_O ,
    input [5:0] pfd_dly_sel ,
    output reg initialed ,


    input [31:0] scan_rd_data ,
    output [31:0] lmx2594_rd_data ,
    output reg lmx2594_rd_data_en ,
    output reg rd_back_end ,
    input freq_end_en ,
    input freq_scan_en ,

    input initial_en ,
    input lmx2594_muxout_1 ,
    input sdi ,
    output spi_oe ,
    output sync ,
    output sck ,
    output sdo
    );


    //OSC_in = 100MHz

    //General Registers R0, R1, & R7

    parameter [0:0] RAMP_EN = 1'b0;//RAMP 模式,0为关闭ramp
    parameter [0:0] VCO_PHASE_SYNC = 1'b0;//相位同步模式

    parameter [1:0] FCAL_HPFD_ADJ = 2'd0;


    // Set this field in accordance to the phase-detector frequency for optimal VCO calibration.
    // 0: fPD ≤ 100 MHz
    // 1: 100 MHz < fPD ≤ 150 MHz
    // 2: 150 MHz < fPD ≤ 200 MHz
    // 3: fPD >200 MHz
    parameter [1:0] FCAL_LPFD_ADJ = 2'd0;
    // Set this field in accordance to the phase detector frequency for optimal VCO calibration.
    // 0: fPD ≥ 10 MHz
    // 1: 10 MHz > fPD ≥ 5 MHz
    // 2: 5 MHz > fPD ≥ 2.5 MHz
    // 3: fPD < 2.5 MHz
    reg FCAL_EN = 1'b0;
    parameter [0:0] FCAL_EN_PARAM = 1'b1;
    // parameter [0:0] FCAL_EN_PARAM = 1'b0;
    parameter [0:0] MUXOUT_LD_SEL = 1'b0;//MUXOUT功能选择,1为锁定检测,0为通信读回。
    reg RESET = 1'b0;//器件复位,1为复位,0为正常。
    parameter RESET_PARAM = 1'b0;//器件复位,1为复位,0为正常。
    parameter [0:0] POWERDOWN = 1'b0;//器件断电,0为正常,1为断电

    parameter [2:0] CAL_CLK_DIV = 3'd0 ; //校准时钟分频系数 Fsmclk = 100MHz;
    parameter [0:0] OUT_MUTE = 1'b0 ; //校准期间是否输出 ,与OUT_FORCE相反,,0为不输出
    parameter [0:0] OUT_FORCE = ~OUT_MUTE ; //校准期间是否输出
    wire [15:0] R0;
    wire [15:0] R1;
    wire [15:0] R7 ;
    //0010 0100 0001 1100 'h241c

    //Normal 241c
    //Reset 2416
    //CAl CLOSE 2414
    assign R0 = freq_end_en ? {RAMP_EN,VCO_PHASE_SYNC,4'b1001,OUT_MUTE,FCAL_HPFD_ADJ,FCAL_LPFD_ADJ,1'b1,FCAL_EN_PARAM,MUXOUT_LD_SEL,RESET_PARAM,POWERDOWN} : 16'h241c;
    // assign R0 = 16'h241c;
    assign R1 = {13'b0000100000001,CAL_CLK_DIV};
    assign R7 = {1'b0,OUT_FORCE,14'b00000010110010};

    //Input Path Registers
    parameter [0:0] OSC_2X = 1'b0 ; //1x 关闭倍频器


    parameter [4:0] MULT = 5'd1 ; //bypass 乘法器
    parameter [7:0] PLL_R = 8'd1 ; //乘法器输入分频器
    parameter [11:0] PLL_R_PRE = 12'd1 ; //乘法器输出分频器

    wire [15:0] R9 ;
    wire [15:0] R10 ;
    wire [15:0] R11 ;
    wire [15:0] R12 ;

    assign R9 = {3'b0,OSC_2X,12'b011000000100};
    assign R10 = {4'd1,MULT,7'b1011000};
    assign R11 = {4'd0,PLL_R,4'd8};
    assign R12 = {4'b0101,PLL_R_PRE};

    //Charge Pump Registers (R13, R14)
    parameter [2:0] CPG = 3'd7;//电荷泵配置
    // Effective charge-pump current. This is the sum of up and down currents.
    // 0: 0 mA
    // 1: 6 mA
    // 2: Reserved
    // 3: 12 mA
    // 4: 3 mA
    // 5: 9 mA
    // 6: Reserved
    // 7: 15 mA
    wire [15:0] R14 ;
    assign R14 = {9'b000111100,CPG,4'b0000};

    //VCO Calibration Registers

    //选择校准辅助模式
    // QUICK_RECAL_EN=0
    // VCO_SEL_FORCE=0
    // VCO_DACISET_FORCE=0
    // VCO_CAPCTRL_FORCE=0

    parameter [7:0] ACAL_CMP_DELAY = 8'd11 ;//ACAL_CMP_DLY > Fsmclk / 10 MHz, If calibration time is of concern,then it is recommended to set this register to ≥ 25.
    parameter [0:0] VCO_DACISET_FORCE = 1'b1 ;//强制使用VCO_DACISET值 //全辅助校准使用
    parameter [0:0] VCO_CAPCTRL_FORCE = 1'b1 ;//强制使用VCO_CAPCTRL值 //全辅助校准使用
    parameter [8:0] VCO_DACISET = 9'd128 ;//VCO_DACISET值,如果强制幅度校准开启,这就是最终的VCO幅度校准值
    reg [8:0] VCO_DACISET_STRT = 9'd250 ;//这设置了VCO幅度校准的初始起点。
    parameter [7:0] VCO_CAPCTRL = 8'd183 ;//VCO_CAPCTRL值,如果强制频带校准开启,这就是最终的VCO频带校准值
    reg [2:0] VCO_SEL = 3'd7 ;//校准起始VCO 0: Not Used 1: VCO1 2: VCO2 3: VCO3 4: VCO4 5: VCO5 6: VCO6 7: VCO7
    parameter [0:0] VCO_SEL_FORCE = 1'b1 ;//强制使用VCO_SEL选择的VCO//全辅助校准使用
    wire [15:0] R4 ;
    wire [15:0] R8 ;
    wire [15:0] R16 ;
    wire [15:0] R17 ;
    wire [15:0] R19 ;
    wire [15:0] R20 ;

    assign R4 = {ACAL_CMP_DELAY,8'b01000011};
    assign R8 = freq_end_en ? {1'b0,VCO_DACISET_FORCE,2'b10,VCO_CAPCTRL_FORCE,11'b0} : 16'h2000;
    assign R16 = {7'b0,scan_rd_data[28:21]}; //VCO_DACISET配置8bit
    // assign R17 = {7'b0,VCO_DACISET_STRT};
    assign R19 = {8'b00100111,scan_rd_data[20:14]}; //VCO_CAPCTRL配置7bit
    assign R20 = {2'b11,scan_rd_data[13:11],VCO_SEL_FORCE,10'b0001001000}; // VCO_SEL配置3bit

    //N Divider, MASH, and Output Registers
    reg [18:0] PLL_N=19'd0;//分频系数,整数部分
    parameter [0:0] MASH_SEED_EN = 1'b0 ;//优化杂散
    reg [5:0] PFD_DLY_SEL = 0 ;
    // parameter [31:0] PLL_DEN = 32'd4194304;
    //parameter [31:0] PLL_DEN = 32'd4294967295;
    parameter [31:0] PLL_DEN = 32'd4194303; //2^22-1 =4194304-1=4194303
    parameter [31:0] MASH_SEED = 32'd0 ;
    reg [31:0] PLL_NUM = 32'd0 ;
    reg [5:0] OUTA_PWR = 6'd31 ;//输出功率调节
    parameter [0:0] OUTB_PD = 1'b1 ;//输出B 关闭 1为关闭
    parameter [0:0] OUTA_PD = 1'b0 ;//输出A 关闭 1为关闭
    parameter [0:0] MASH_RESET_N = 1'b1 ;//分数模式,0为整数模式, MASH复位
    //parameter [2:0] MASH_ORDER = 3'd4 ;//0为整数模式
    reg [1:0] OUTA_MUX = 2'd1 ;//A通道输出选择
    // 0: Channel divider
    // 1: VCO
    // 2: Reserved
    // 3: High impedance
    parameter [1:0] OUT_ISET = 2'd0 ;//输出功率boost ,0为最大boost,3为不boost
    parameter [5:0] OUTB_PWR = 6'b011111 ;//输出功率设置
    parameter [1:0] OUTB_MUX = 2'd0 ;//B通道输出选择



    wire [15:0] R34 ;
    wire [15:0] R36 ;
    wire [15:0] R37 ;
    wire [15:0] R38 ;
    wire [15:0] R39 ;
    wire [15:0] R40 ;
    wire [15:0] R41 ;
    wire [15:0] R42 ;
    wire [15:0] R43 ;
    wire [15:0] R44 ;
    wire [15:0] R45 ;
    wire [15:0] R46 ;

    assign R34 = {13'b0,PLL_N[18:16]};
    assign R36 = PLL_N[15:0];
    assign R37 = {MASH_SEED_EN,1'b0,PFD_DLY_SEL,8'b00000100};
    assign R38 = PLL_DEN[31:16];
    assign R39 = PLL_DEN[15:0 ];
    assign R40 = MASH_SEED[31:16];
    assign R41 = MASH_SEED[15:0 ];
    assign R42 = PLL_NUM[31:16];
    assign R43 = PLL_NUM[15:0 ];
    assign R44 = {2'b0,OUTA_PWR,OUTB_PD,OUTA_PD,MASH_RESET_N,2'b0,MASH_ORDER_O};
    assign R45 = {3'b110,OUTA_MUX,OUT_ISET,3'b011,OUTB_PWR};
    assign R46 = {14'b00000111111111,OUTB_MUX};

    //Lock Detect Registers

    parameter LD_TYPE = 1'b1;//锁相类型
    parameter [15:0] LD_DLY = 16'd1000;//VCO校准成功之后的延时

    wire [15:0] R59 ;
    wire [15:0] R60 ;

    assign R59 = {15'b0,LD_TYPE};
    assign R60 = LD_DLY;

    parameter [31:0] MASH_RST_COUNT = 32'd0;

    wire [15:0] R69 ;
    wire [15:0] R70 ;

    assign R69 = MASH_RST_COUNT[31:16];
    assign R70 = MASH_RST_COUNT[15:0];

    //CHANNEL Divider Registers

    reg SEG1_EN = 0;//Enable driver buffer for CHDIV > 2 0: Disabled (only valid for CHDIV = 2) 1: Enabled (use for CHDIV > 2)
    reg [4:0] CHDIV = 0;
    // VCO divider value
    // 0: 2
    // 1: 4
    // 2: 6
    // 3: 8
    // 4: 12
    // 5: 16
    // 6: 24
    // 7: 32
    // 8: 48
    // 9: 64
    // 10: 72
    // 11: 96
    // 12: 128
    // 13: 192
    // 14: 256
    // 15: 384
    // 16: 512
    // 17: 768
    // 18-31: Reserved

    wire [15:0] R31 ;
    wire [15:0] R75 ;

    assign R31 = {1'b0,SEG1_EN,14'b00001111101100};
    assign R75 = {5'b00001,CHDIV,6'b000000};

    //VCO_CAPCTRL_STRT

    parameter [0:0] QUICK_RECAL_EN = 1'b0;
    reg [7:0] VCO_CAPCTRL_STRT = 8'd128;

    wire [15:0] R78;
    // assign R78 = {4'b0,1'b0,1'b0,QUICK_RECAL_EN,VCO_CAPCTRL_STRT,1'b1};

    // wire [15:0] R0 ;
    // wire [15:0] R1 ;
    // wire [15:0] R4 ;
    // wire [15:0] R7 ;
    // wire [15:0] R8 ;
    // wire [15:0] R9 ;
    // wire [15:0] R10 ;
    // wire [15:0] R11 ;
    // wire [15:0] R12 ;
    // wire [15:0] R14 ;
    // wire [15:0] R16 ;
    // wire [15:0] R17 ;
    // wire [15:0] R19 ;
    // wire [15:0] R20 ;
    // wire [15:0] R34 ;
    // wire [15:0] R36 ;
    // wire [15:0] R37 ;
    // wire [15:0] R38 ;
    // wire [15:0] R39 ;
    // wire [15:0] R40 ;
    // wire [15:0] R41 ;
    // wire [15:0] R42 ;
    // wire [15:0] R43 ;
    // wire [15:0] R44 ;
    // wire [15:0] R45 ;
    // wire [15:0] R46 ;
    // wire [15:0] R59 ;
    // wire [15:0] R60 ;
    // wire [15:0] R69 ;
    // wire [15:0] R70 ;
    // wire [15:0] R78 ;

    // localparam IDEL = 5'd0 ;
    // localparam INI = 5'd1 ;
    // localparam FREQ_RE = 5'd2 ;
    // localparam RD_BACK1 = 5'd3 ;
    // localparam RD_BACK2 = 5'd4 ;
    // localparam RD_BACK3 = 5'd5 ;
    // localparam BOOT_DELAY = 5'd6 ;
    // localparam INI_WAIT = 5'd7 ;
    // localparam INI_END = 5'd8 ;
    // localparam DEVICE_RESET = 5'd9 ;

    localparam IDEL = 5'd0 ;
    localparam INI = 5'd1 ;
    localparam INI_WAIT = 5'd2 ;
    localparam INI_END = 5'd3 ;
    localparam FREQ_RE = 5'd4 ;
    localparam RD_BACK_READY = 5'd5 ;
    localparam RD_BACK = 5'd6 ;
    localparam RD_BACK_ALL = 5'd7 ;


    always @(posedge clk_in or negedge rst_n) begin
    if(~rst_n) begin
    MASH_ORDER_O <= 4;
    end
    else if (freq_target_en && freq_target == 32'd10470_000) begin//freq_target rf计算出来的 (本振频率) 不能以rf频率去判断
    MASH_ORDER_O <= 3;
    end
    else if (freq_target_en && freq_target != 32'd10470_000) begin//freq_target rf计算出来的 (本振频率) 不能以rf频率去判断
    MASH_ORDER_O <= 4;
    end
    else begin
    MASH_ORDER_O <= MASH_ORDER_O;
    end
    end

    always @(posedge clk_in or negedge rst_n)
    if(~rst_n)
    OUTA_PWR <= 'd15;
    else
    OUTA_PWR <= out_pwr;

    always @(posedge clk_in or negedge rst_n)
    if(~rst_n)
    PFD_DLY_SEL <= 'd0;
    else
    PFD_DLY_SEL <= pfd_dly_sel;

    always @(posedge clk_in or negedge rst_n)
    if(~rst_n) begin
    VCO_CAPCTRL_STRT <= 8'd128;
    VCO_DACISET_STRT <= 9'd250;
    VCO_SEL <= 'd7;
    end else if(vco_param_en) begin
    VCO_CAPCTRL_STRT <= vco_capctrl_strt;
    VCO_DACISET_STRT <= vco_daciset_strt;
    VCO_SEL <= vco_sel;
    end else begin
    VCO_CAPCTRL_STRT <= VCO_CAPCTRL_STRT;
    VCO_DACISET_STRT <= VCO_DACISET_STRT;
    VCO_SEL <= VCO_SEL;
    end

    always @(posedge clk_in or negedge rst_n)
    if(~rst_n) begin
    PLL_N <= 'd0;
    PLL_NUM <= 'd0;
    end else if(pll_en) begin
    PLL_N <= pll_n;
    PLL_NUM <= pll_num;
    end else begin
    PLL_N <= PLL_N;
    PLL_NUM <= PLL_NUM;
    end

    always @(posedge clk_in or negedge rst_n)
    if(~rst_n) begin
    CHDIV <= 'd0;
    SEG1_EN <= 'd0;
    OUTA_MUX <= 'd1;
    end else begin
    CHDIV <= chdiv ;
    SEG1_EN <= seg1_en ;
    OUTA_MUX <= outa_mux ;
    end

    reg ini_busy;
    reg lmx2594_config_en;
    wire lmx2594_config_end;

    reg lmx2594_rw;
    reg [6:0] lmx2594_addr;
    reg [15:0] lmx2594_data;
    wire [23:0] lmx2594_config_sum;
    assign lmx2594_config_sum = {lmx2594_rw,lmx2594_addr,lmx2594_data};

    wire [15:0] lmx2594_rded_data;

    reg [7:0] cnt_beat;
    reg flg_end;

    reg test_en2;
    // FCAL_EN = 1'b1;
    // RESET = 1'b0;//器件复位,1为复位,0为正常。

    reg freq_re_config;
    always @(posedge clk_in or negedge rst_n) begin
    if(~rst_n)
    freq_re_config <= 1'b0;
    else if(vco_param_en == 1'b0)begin
    freq_re_config <= freq_vco_scan_en;
    end else begin
    freq_re_config <= vco_param_en;
    end
    end

    reg [4:0] state_lmx2594_config;

    reg flag_test;
    reg flag_test1 = 0;
    reg flag_test2 = 0;

    reg [31:0] ini_wait_cnt = 'd0;

    reg first_reg_flag;

    reg [31:0] cnt_ready;
    localparam MAX = 50_000_000;

    always @(posedge clk_in or negedge rst_n)
    if(~rst_n) begin

    state_lmx2594_config <= IDEL;
    ini_busy <= 1'b0;
    initialed <= 1'b0;
    RESET <= 1'b1;
    FCAL_EN <= 1'b0;
    lmx2594_config_en <= 1'b0;
    cnt_beat <= 'd0;
    lmx2594_rw <= 1'b0;
    lmx2594_addr <= 8'd0;
    lmx2594_data <= 16'd0;
    rd_back_end <= 1'b0;
    flag_test <= 1'b0;
    first_reg_flag <= 1'b0;
    cnt_ready <= 32'd0;
    end else begin
    case(state_lmx2594_config)
    IDEL:begin
    first_reg_flag <= 1'b0;
    rd_back_end <= 1'b0;
    if(ini_en || initial_en ) begin
    state_lmx2594_config <= INI;
    ini_busy <= 1'b1;
    RESET <= 1'b1;
    FCAL_EN <= 1'b0;
    flag_test <= 1'b1;
    flag_test1 <= 1'b0;
    flag_test2 <= 1'b1;
    end else if(freq_re_config) begin
    state_lmx2594_config <= FREQ_RE;
    flag_test <= 1'b1;
    flag_test1 <= 1'b1;
    flag_test2 <= 1'b0;
    end else begin
    flag_test <= 1'b0;
    flag_test1 <= 1'b0;
    flag_test2 <= 1'b0;
    end
    end
    INI:begin//log_wave -r /*

    if(lmx2594_config_end) begin
    cnt_beat <= cnt_beat + 1'b1;
    lmx2594_config_en <= 1'b1;
    end else if(first_reg_flag == 1'b0 && cnt_beat == 'd0) begin
    lmx2594_config_en <= 1'b1;
    first_reg_flag <= 1'b1;
    end else begin
    cnt_beat <= cnt_beat;
    lmx2594_config_en <= 1'b0;
    end

    case(cnt_beat)
    'd115 :begin state_lmx2594_config <= INI_WAIT; cnt_beat <= 0; initialed <= 1'b0;first_reg_flag <= 1'b0;end
    'd114 :begin lmx2594_addr <= 7'h00 ; lmx2594_data <= 16'h241c ; end//reg 0
    'd113 :begin lmx2594_addr <= 7'h01 ; lmx2594_data <= R1 ; end//reg 1
    'd112 :begin lmx2594_addr <= 7'h02 ; lmx2594_data <= 16'h0500 ; end//reg 1
    'd111 :begin lmx2594_addr <= 7'h03 ; lmx2594_data <= 16'h0642 ; end//reg 1
    'd110 :begin lmx2594_addr <= 7'h04 ; lmx2594_data <= R4 ; end//reg 4
    'd109 :begin lmx2594_addr <= 7'h05 ; lmx2594_data <= 16'h00C8 ; end//reg 4
    'd108 :begin lmx2594_addr <= 7'h06 ; lmx2594_data <= 16'hC802 ; end//reg 4
    'd107 :begin lmx2594_addr <= 7'h07 ; lmx2594_data <= R7; end//reg 7
    'd106 :begin lmx2594_addr <= 7'h08 ; lmx2594_data <= 16'h2000 ; end//reg 8
    'd105 :begin lmx2594_addr <= 7'h09 ; lmx2594_data <= R9 ; end//reg 9
    'd104 :begin lmx2594_addr <= 7'h0A ; lmx2594_data <= R10 ; end//reg 10
    'd103 :begin lmx2594_addr <= 7'h0B ; lmx2594_data <= R11 ; end//reg 11
    'd102 :begin lmx2594_addr <= 7'h0C ; lmx2594_data <= R12; end//reg 12
    'd101 :begin lmx2594_addr <= 7'h0D ; lmx2594_data <= 16'h4000 ; end//reg 13
    'd100 :begin lmx2594_addr <= 7'h0E ; lmx2594_data <= R14 ; end//reg 14 电荷泵 15ma
    'd99 :begin lmx2594_addr <= 7'h0F ; lmx2594_data <= 16'h064F ; end//reg 15
    'd98 :begin lmx2594_addr <= 7'h10 ; lmx2594_data <= 16'h0080 ; end//reg 16
    'd97 :begin lmx2594_addr <= 7'h11 ; lmx2594_data <= 16'h0046 ; end//reg 17
    'd96 :begin lmx2594_addr <= 7'h12 ; lmx2594_data <= 16'h0064 ; end//reg 18
    'd95 :begin lmx2594_addr <= 7'h13 ; lmx2594_data <= 16'h27B7 ; end//reg 19
    'd94 :begin lmx2594_addr <= 7'h14 ; lmx2594_data <= 16'hE848 ; end//reg 20
    'd93 :begin lmx2594_addr <= 7'h15 ; lmx2594_data <= 16'h0401 ; end//reg 21
    'd92 :begin lmx2594_addr <= 7'h16 ; lmx2594_data <= 16'h0001 ; end//reg 22
    'd91 :begin lmx2594_addr <= 7'h17 ; lmx2594_data <= 16'h007C ; end//reg 23
    'd90 :begin lmx2594_addr <= 7'h18 ; lmx2594_data <= 16'h071A ; end//reg 24
    'd89 :begin lmx2594_addr <= 7'h19 ; lmx2594_data <= 16'h0C2B ; end//reg 25
    'd88 :begin lmx2594_addr <= 7'h1A ; lmx2594_data <= 16'h0DB0 ; end//reg 26
    'd87 :begin lmx2594_addr <= 7'h1B ; lmx2594_data <= 16'h0002 ; end//reg 27
    'd86 :begin lmx2594_addr <= 7'h1C ; lmx2594_data <= 16'h0488 ; end//reg 28
    'd85 :begin lmx2594_addr <= 7'h1D ; lmx2594_data <= 16'h318C ; end//reg 29
    'd84 :begin lmx2594_addr <= 7'h1E ; lmx2594_data <= 16'h318C ; end//reg 30
    'd83 :begin lmx2594_addr <= 7'h1F ; lmx2594_data <= 16'h43EC ; end//reg 31
    'd82 :begin lmx2594_addr <= 7'h20 ; lmx2594_data <= 16'h0393 ; end//reg 32
    'd81 :begin lmx2594_addr <= 7'h21 ; lmx2594_data <= 16'h1E21 ; end//reg 33
    'd80 :begin lmx2594_addr <= 7'h22 ; lmx2594_data <= 16'h0000 ; end//reg 34
    'd79 :begin lmx2594_addr <= 7'h23 ; lmx2594_data <= 16'h0004 ; end//reg 35
    'd78 :begin lmx2594_addr <= 7'h24 ; lmx2594_data <= 16'h007E ; end//reg 36
    'd77 :begin lmx2594_addr <= 7'h25 ; lmx2594_data <= 16'h0304 ; end//reg 37
    'd76 :begin lmx2594_addr <= 7'h26 ; lmx2594_data <= 16'h0000 ; end//reg 38
    'd75 :begin lmx2594_addr <= 7'h27 ; lmx2594_data <= 16'h2710 ; end//reg 39
    'd74 :begin lmx2594_addr <= 7'h28 ; lmx2594_data <= 16'h0000 ; end//reg 40
    'd73 :begin lmx2594_addr <= 7'h29 ; lmx2594_data <= 16'h0000 ; end//reg 41
    'd72 :begin lmx2594_addr <= 7'h2A ; lmx2594_data <= 16'h0000 ; end//reg 42
    'd71 :begin lmx2594_addr <= 7'h2B ; lmx2594_data <= 16'h0000 ; end//reg 43
    'd70 :begin lmx2594_addr <= 7'h2C ; lmx2594_data <= R44 ; end//reg 44 20a3//h2C20a3:outa_en;h2C2063:outa_en;
    'd69 :begin lmx2594_addr <= 7'h2D ; lmx2594_data <= 16'hC0F2 ; end//reg 45 outa 分频选择or vco输出
    'd68 :begin lmx2594_addr <= 7'h2E ; lmx2594_data <= R46 ; end//reg 46 //07fc outb 分频选择or vco输出
    'd67 :begin lmx2594_addr <= 7'h2F ; lmx2594_data <= 16'h0300 ; end//reg 47
    'd66 :begin lmx2594_addr <= 7'h30 ; lmx2594_data <= 16'h0300 ; end//reg 48
    'd65 :begin lmx2594_addr <= 7'h31 ; lmx2594_data <= 16'h4180 ; end//reg 49
    'd64 :begin lmx2594_addr <= 7'h32 ; lmx2594_data <= 16'h0000 ; end//reg 50
    'd63 :begin lmx2594_addr <= 7'h33 ; lmx2594_data <= 16'h0080 ; end//reg 51
    'd62 :begin lmx2594_addr <= 7'h34 ; lmx2594_data <= 16'h0820 ; end//reg 52
    'd61 :begin lmx2594_addr <= 7'h35 ; lmx2594_data <= 16'h0000 ; end//reg 53
    'd60 :begin lmx2594_addr <= 7'h36 ; lmx2594_data <= 16'h0000 ; end//reg 54
    'd59 :begin lmx2594_addr <= 7'h37 ; lmx2594_data <= 16'h0000 ; end//reg 55
    'd58 :begin lmx2594_addr <= 7'h38 ; lmx2594_data <= 16'h0000 ; end//reg 56
    'd57 :begin lmx2594_addr <= 7'h39 ; lmx2594_data <= 16'h0020 ; end//reg 57
    'd56 :begin lmx2594_addr <= 7'h3A ; lmx2594_data <= 16'h8001 ; end//reg 58
    'd55 :begin lmx2594_addr <= 7'h3B ; lmx2594_data <= 16'h0001 ; end//reg 59
    'd54 :begin lmx2594_addr <= 7'h3C ; lmx2594_data <= 16'h0000 ; end//reg 60
    'd53 :begin lmx2594_addr <= 7'h3D ; lmx2594_data <= 16'h00A8 ; end//reg 61
    'd52 :begin lmx2594_addr <= 7'h3E ; lmx2594_data <= 16'h0322 ; end//reg 62
    'd51 :begin lmx2594_addr <= 7'h3F ; lmx2594_data <= 16'h0000 ; end//reg 63
    'd50 :begin lmx2594_addr <= 7'h40 ; lmx2594_data <= 16'h1388 ; end//reg 64
    'd49 :begin lmx2594_addr <= 7'h41 ; lmx2594_data <= 16'h0000 ; end//reg 65
    'd48 :begin lmx2594_addr <= 7'h42 ; lmx2594_data <= 16'h01F4 ; end//reg 66
    'd47 :begin lmx2594_addr <= 7'h43 ; lmx2594_data <= 16'h0000 ; end//reg 67
    'd46 :begin lmx2594_addr <= 7'h44 ; lmx2594_data <= 16'h03E8 ; end//reg 68
    'd45 :begin lmx2594_addr <= 7'h45 ; lmx2594_data <= 16'h0000 ; end//reg 69
    'd44 :begin lmx2594_addr <= 7'h46 ; lmx2594_data <= 16'hC350 ; end//reg 70
    'd43 :begin lmx2594_addr <= 7'h47 ; lmx2594_data <= 16'h0081 ; end//reg 71 00c9
    'd42 :begin lmx2594_addr <= 7'h48 ; lmx2594_data <= 16'h0001 ; end//reg 72 0003
    'd41 :begin lmx2594_addr <= 7'h49 ; lmx2594_data <= 16'h003F ; end//reg 73
    'd40 :begin lmx2594_addr <= 7'h4A ; lmx2594_data <= 16'h0000 ; end//reg 74
    'd39 :begin lmx2594_addr <= 7'h4B ; lmx2594_data <= 16'h0800 ; end//reg 75 //分频比 4B0800 2分频 4b0840 4分频
    'd38 :begin lmx2594_addr <= 7'h4C ; lmx2594_data <= 16'h000C; end//reg 76
    'd37 :begin lmx2594_addr <= 7'h4D ; lmx2594_data <= 16'h0000 ; end//reg 77
    'd36 :begin lmx2594_addr <= 7'h4E ; lmx2594_data <= 16'h00AB ; end//reg 78 0003
    'd35 :begin lmx2594_addr <= 7'h4F ; lmx2594_data <= 16'h0000 ; end//reg 79 0026
    'd34 :begin lmx2594_addr <= 7'h50 ; lmx2594_data <= 16'h0000 ; end//reg 80 6666
    'd33 :begin lmx2594_addr <= 7'h51 ; lmx2594_data <= 16'h0000 ; end//reg 81
    'd32 :begin lmx2594_addr <= 7'h52 ; lmx2594_data <= 16'h0000 ; end//reg 82 1E00
    'd31 :begin lmx2594_addr <= 7'h53 ; lmx2594_data <= 16'h0000 ; end//reg 83
    'd30 :begin lmx2594_addr <= 7'h54 ; lmx2594_data <= 16'h0000 ; end//reg 84 RAMP_LIMIT_LOW[32] 0001
    'd29 :begin lmx2594_addr <= 7'h55 ; lmx2594_data <= 16'h0000 ; end//reg 85 //RAMP_LIMIT_LOW[31:16] D300
    'd28 :begin lmx2594_addr <= 7'h56 ; lmx2594_data <= 16'h0000 ; end//reg 86
    'd27 :begin lmx2594_addr <= 7'h57 ; lmx2594_data <= 16'h0000 ; end//reg 87
    'd26 :begin lmx2594_addr <= 7'h58 ; lmx2594_data <= 16'h0000 ; end//reg 88
    'd25 :begin lmx2594_addr <= 7'h59 ; lmx2594_data <= 16'h0000 ; end//reg 89
    'd24 :begin lmx2594_addr <= 7'h5A ; lmx2594_data <= 16'h0000 ; end//reg 90
    'd23 :begin lmx2594_addr <= 7'h5B ; lmx2594_data <= 16'h0000 ; end//reg 91
    'd22 :begin lmx2594_addr <= 7'h5C ; lmx2594_data <= 16'h0000 ; end//reg 92
    'd21 :begin lmx2594_addr <= 7'h5D ; lmx2594_data <= 16'h0000 ; end//reg 93
    'd20 :begin lmx2594_addr <= 7'h5E ; lmx2594_data <= 16'h0000 ; end//reg 94
    'd19 :begin lmx2594_addr <= 7'h5F ; lmx2594_data <= 16'h0000 ; end//reg 95
    'd18 :begin lmx2594_addr <= 7'h60 ; lmx2594_data <= 16'h0000 ; end//reg 96
    'd17 :begin lmx2594_addr <= 7'h61 ; lmx2594_data <= 16'h0888 ; end//reg 97
    'd16 :begin lmx2594_addr <= 7'h62 ; lmx2594_data <= 16'h0000 ; end//reg 98 //RAMP0_INC 0200
    'd15 :begin lmx2594_addr <= 7'h63 ; lmx2594_data <= 16'h0000 ; end//reg 99
    'd14 :begin lmx2594_addr <= 7'h64 ; lmx2594_data <= 16'h0000 ; end//reg 100
    'd13 :begin lmx2594_addr <= 7'h65 ; lmx2594_data <= 16'h0011 ; end//reg 101
    'd12 :begin lmx2594_addr <= 7'h66 ; lmx2594_data <= 16'h0000 ; end//reg 102 //RAMP1_INC 3F00
    'd11 :begin lmx2594_addr <= 7'h67 ; lmx2594_data <= 16'h0000 ; end//reg 103
    'd10 :begin lmx2594_addr <= 7'h68 ; lmx2594_data <= 16'h0000 ; end//reg 104
    'd9 :begin lmx2594_addr <= 7'h69 ; lmx2594_data <= 16'h0021 ; end//reg 105
    'd8 :begin lmx2594_addr <= 7'h6A ; lmx2594_data <= 16'h0000 ; end//reg 106
    'd7 :begin lmx2594_addr <= 7'h6B ; lmx2594_data <= 16'h0000 ; end//reg 106
    'd6 :begin lmx2594_addr <= 7'h6C ; lmx2594_data <= 16'h0000 ; end//reg 106
    'd5 :begin lmx2594_addr <= 7'h6D ; lmx2594_data <= 16'h0000 ; end//reg 106
    'd4 :begin lmx2594_addr <= 7'h6E ; lmx2594_data <= 16'h0000 ; end//reg 110
    'd3 :begin lmx2594_addr <= 7'h6F ; lmx2594_data <= 16'h0000 ; end//reg 111
    'd2 :begin lmx2594_addr <= 7'h70 ; lmx2594_data <= 16'h0000 ; end//reg 112
    'd1 :begin lmx2594_addr <= 7'h00 ; lmx2594_data <= 16'h241C ; end //配置r0 RESET = 0
    'd0 :begin lmx2594_addr <= 7'h00 ; lmx2594_data <= 16'h2416 ; end ////配置r0 RESET= 1
    endcase
    end
    INI_WAIT: begin
    if(ini_wait_cnt == 30'd500000) begin
    state_lmx2594_config <=INI_END;
    end else begin
    ini_wait_cnt <= ini_wait_cnt+1'b1;
    state_lmx2594_config <= state_lmx2594_config;
    end
    end
    INI_END : begin
    if(lmx2594_config_end) begin
    cnt_beat <= cnt_beat + 1'b1;
    lmx2594_config_en <= 1'b1;
    end else if(first_reg_flag == 1'b0 && cnt_beat == 'd0) begin
    lmx2594_config_en <= 1'b1;
    first_reg_flag <= 1'b1;
    end else begin
    cnt_beat <= cnt_beat;
    lmx2594_config_en <= 1'b0;
    end
    case(cnt_beat)
    'd1 :begin state_lmx2594_config <= IDEL; cnt_beat <= 0; initialed <= 1'b1;first_reg_flag <= 1'b0;end
    'd0 :begin lmx2594_addr <= 7'h00 ; lmx2594_data <= 16'h241c; end ////配置r0 fcal_en = 1
    endcase
    end
    FREQ_RE://无辅助校准
    begin
    if(freq_end_en == 1'b1) begin
    if(lmx2594_config_end)
    begin
    cnt_beat <= cnt_beat + 1'b1;
    lmx2594_config_en <= 1'b1;
    end
    else if(first_reg_flag == 1'b0 && cnt_beat == 8'd0)
    begin
    lmx2594_config_en <= 1'b1;
    first_reg_flag <= 1'b1;
    end
    else
    begin
    cnt_beat <= cnt_beat;
    lmx2594_config_en <= 1'b0;
    end
    case(cnt_beat)
    8'd12 :
    begin
    state_lmx2594_config <=IDEL;
    cnt_beat <= 8'd0;
    first_reg_flag <= 1'b0;
    flg_end <= 1'b1;
    end
    'd11 :begin state_lmx2594_config <=RD_BACK_READY; cnt_beat <= 0;first_reg_flag <= 1'b0;end
    'd10 :begin lmx2594_addr <= 7'd0 ; lmx2594_data <= R0;end
    'd9 :begin lmx2594_addr <= 7'd31; lmx2594_data <= R31 ;end
    'd8 :begin lmx2594_addr <= 7'd34; lmx2594_data <= R34 ;end
    'd7 :begin lmx2594_addr <= 7'd36; lmx2594_data <= R36 ;end
    'd6 :begin lmx2594_addr <= 7'd37; lmx2594_data <= R37 ;end
    'd5 :begin lmx2594_addr <= 7'd38; lmx2594_data <= R38 ;end
    'd4 :begin lmx2594_addr <= 7'd39; lmx2594_data <= R39 ;end
    'd3 :begin lmx2594_addr <= 7'd42; lmx2594_data <= R42 ;end
    'd2 :begin lmx2594_addr <= 7'd43; lmx2594_data <= R43 ;end
    'd1 :begin lmx2594_addr <= 7'd44; lmx2594_data <= R44 ;end
    'd0 :begin lmx2594_addr <= 7'd45; lmx2594_data <= R45 ;end

    // 'd14 :begin lmx2594_addr <= 7'd0 ; lmx2594_data <= R0;end
    // 'd13 :begin lmx2594_addr <= 7'd17; lmx2594_data <= R17 ;end
    // 'd12 :begin lmx2594_addr <= 7'd20; lmx2594_data <= R20 ;end
    // 'd11 :begin lmx2594_addr <= 7'd31; lmx2594_data <= R31 ;end
    // 'd10 :begin lmx2594_addr <= 7'd34; lmx2594_data <= R34 ;end
    // 'd9 :begin lmx2594_addr <= 7'd36; lmx2594_data <= R36 ;end
    // 'd8 :begin lmx2594_addr <= 7'd37; lmx2594_data <= R37 ;end
    // 'd7 :begin lmx2594_addr <= 7'd38; lmx2594_data <= R38 ;end
    // 'd6 :begin lmx2594_addr <= 7'd39; lmx2594_data <= R39 ;end
    // 'd5 :begin lmx2594_addr <= 7'd42; lmx2594_data <= R42 ;end
    // 'd4 :begin lmx2594_addr <= 7'd43; lmx2594_data <= R43 ;end
    // 'd3 :begin lmx2594_addr <= 7'd44; lmx2594_data <= R44 ;end
    // 'd2 :begin lmx2594_addr <= 7'd45; lmx2594_data <= R45 ;end
    // 'd1 :begin lmx2594_addr <= 7'd75; lmx2594_data <= R75 ;end
    // 'd0 :begin lmx2594_addr <= 7'd78; lmx2594_data <= R78 ;end



    endcase
    end
    else if(freq_end_en == 1'b0) begin
    if(lmx2594_config_end)
    begin
    cnt_beat <= cnt_beat + 1'b1;
    lmx2594_config_en <= 1'b1;
    end
    else if(first_reg_flag == 1'b0 && cnt_beat == 8'd0)
    begin
    lmx2594_config_en <= 1'b1;
    first_reg_flag <= 1'b1;
    end
    else
    begin
    cnt_beat <= cnt_beat;
    lmx2594_config_en <= 1'b0;
    end
    case(cnt_beat)
    8'd14 :
    begin
    state_lmx2594_config <= IDEL; //IDLE
    cnt_beat <= 8'd0;
    first_reg_flag <= 1'b0;
    flg_end <= 1'b1;
    end
    'd13 :begin lmx2594_addr <= 7'd08; lmx2594_data <= R8 ;end
    'd12 :begin lmx2594_addr <= 7'd16; lmx2594_data <= R16 ;end
    'd11 :begin lmx2594_addr <= 7'd19; lmx2594_data <= R19 ;end
    'd10 :begin lmx2594_addr <= 7'd20; lmx2594_data <= R20 ;end
    'd9 :begin lmx2594_addr <= 7'd31; lmx2594_data <= R31 ;end
    'd8 :begin lmx2594_addr <= 7'd34; lmx2594_data <= R34 ;end
    'd7 :begin lmx2594_addr <= 7'd36; lmx2594_data <= R36 ;end
    'd6 :begin lmx2594_addr <= 7'd37; lmx2594_data <= R37 ;end
    'd5 :begin lmx2594_addr <= 7'd38; lmx2594_data <= R38 ;end
    'd4 :begin lmx2594_addr <= 7'd39; lmx2594_data <= R39 ;end
    'd3 :begin lmx2594_addr <= 7'd42; lmx2594_data <= R42 ;end
    'd2 :begin lmx2594_addr <= 7'd43; lmx2594_data <= R43 ;end
    'd1 :begin lmx2594_addr <= 7'd44; lmx2594_data <= R44 ;end
    'd0 :begin lmx2594_addr <= 7'd45; lmx2594_data <= R45 ;end

    endcase
    end
    end



    RD_BACK_READY: begin
    if(cnt_ready < MAX) begin
    cnt_ready <= cnt_ready + 1'b1;
    end
    else if(cnt_ready == MAX ) begin
    cnt_ready <= 0;
    state_lmx2594_config <= RD_BACK;
    lmx2594_config_en <= 1'b1;
    // lmx2594_addr <= 7'h006E;lmx2594_data <= 16'd0;
    // lmx2594_rw <= 1'b1;
    end
    end
    RD_BACK: begin
    if(lmx2594_config_end ) begin
    cnt_beat <= cnt_beat + 1'b1;
    lmx2594_config_en <= 1'b1;
    end
    else begin
    lmx2594_config_en <= 1'b0;
    end
    case(cnt_beat)
    // 8'd3 :begin state_lmx2594_config <= IDEL;cnt_beat <= 8'd0;lmx2594_config_en <= 1'b0;rd_back_end <= 1'b1;lmx2594_rw <= 1'b0;end
    // 8'd2 :begin lmx2594_addr <= 7'h0070;lmx2594_data <= 16'd0;lmx2594_rw <= 1'b1;end
    // 8'd1 :begin lmx2594_addr <= 7'h006F;lmx2594_data <= 16'd0;lmx2594_rw <= 1'b1;end
    // 8'd0 :begin lmx2594_addr <= 7'h006E;lmx2594_data <= 16'd0;lmx2594_rw <= 1'b1;end

    8'd7 :begin state_lmx2594_config <= IDEL;cnt_beat <= 8'd0;lmx2594_config_en <= 1'b0;rd_back_end <= 1'b1;lmx2594_rw <= 1'b0;end
    8'd6 :begin lmx2594_addr <= 7'h0070;lmx2594_data <= 16'd0;lmx2594_rw <= 1'b1;end
    8'd5 :begin lmx2594_addr <= 7'h006F;lmx2594_data <= 16'd0;lmx2594_rw <= 1'b1;end
    8'd4 :begin lmx2594_addr <= 7'h006E;lmx2594_data <= 16'd0;lmx2594_rw <= 1'b1;end
    8'd3 :begin lmx2594_addr <= 7'h0000;lmx2594_data <= 16'd0;lmx2594_rw <= 1'b1;end
    8'd2 :begin lmx2594_addr <= 7'h006d;lmx2594_data <= 16'd0;lmx2594_rw <= 1'b1;end
    8'd1 :begin lmx2594_addr <= 7'h006c;lmx2594_data <= 16'd0;lmx2594_rw <= 1'b1;end
    8'd0 :begin lmx2594_addr <= 7'h006b;lmx2594_data <= 16'd0;lmx2594_rw <= 1'b1;end

    endcase
    end
    endcase
    end



    reg [15:0] lmx2594_rd_data_1;
    reg [15:0] lmx2594_rd_data_2;
    reg [15:0] lmx2594_rd_data_3;
    wire [31:0] lmx2594_rd_data;
    assign lmx2594_rd_data = {lmx2594_rd_data_1[10:0],lmx2594_rd_data_2[9:0],lmx2594_rd_data_3[10:0]};

    always @(posedge clk_in or negedge rst_n) begin //
    if(~rst_n)begin //
    lmx2594_rd_data_1 <= 'd0 ;
    lmx2594_rd_data_2 <= 'd0 ;
    lmx2594_rd_data_3 <= 'd0 ;
    lmx2594_rd_data_en <= 'd0 ; //
    end
    else if(lmx2594_config_end && state_lmx2594_config == RD_BACK && cnt_beat == 8'd0)begin //1
    lmx2594_rd_data_1 <= lmx2594_rded_data ;
    lmx2594_rd_data_2 <= lmx2594_rd_data_2 ;
    lmx2594_rd_data_3 <= lmx2594_rd_data_3;
    lmx2594_rd_data_en <= 'd0 ;
    end
    else if(lmx2594_config_end && state_lmx2594_config == RD_BACK && cnt_beat == 8'd1)begin //2 // end else if(lmx2594_config_end && state_lmx2594_config == RD_BACK && cnt_beat == 2)begin
    lmx2594_rd_data_en <= 'd0 ;
    lmx2594_rd_data_1 <= lmx2594_rd_data_1 ;
    lmx2594_rd_data_2 <= lmx2594_rded_data ;
    lmx2594_rd_data_3 <= lmx2594_rd_data_3;

    end
    else if(lmx2594_config_end && state_lmx2594_config == RD_BACK && cnt_beat == 8'd2)begin // end else if(lmx2594_config_end && state_lmx2594_config == RD_BACK && cnt_beat == 2)begin
    lmx2594_rd_data_en <= 'd1 ;
    lmx2594_rd_data_1 <= lmx2594_rd_data_1 ;
    lmx2594_rd_data_2 <= lmx2594_rd_data_2 ;
    lmx2594_rd_data_3 <= lmx2594_rded_data;
    end
    // else if(state_lmx2594_config == RD_BACK && cnt_beat == 8'd3)begin
    // lmx2594_rd_data_en <= 'd1 ; //回读完成,使能拉高
    // lmx2594_rd_data_1 <= lmx2594_rd_data_1 ;
    // lmx2594_rd_data_2 <= lmx2594_rd_data_2 ;
    // lmx2594_rd_data_3 <= lmx2594_rd_data_3;
    // end
    else begin //
    lmx2594_rd_data_en <= 0;//
    lmx2594_rd_data_1 <= lmx2594_rd_data_1 ;
    lmx2594_rd_data_2 <= lmx2594_rd_data_2 ;
    lmx2594_rd_data_3 <= lmx2594_rd_data_3;
    end
    end


    wire spi_oe;
    wire spi_oe_d;

    lmx2594_spi_24bit u1(
    .clk_sys (clk_in ), //40M
    .rst_n (rst_n ),
    .data (lmx2594_config_sum ), //配置数据
    .valid (lmx2594_config_en ), //使能信号
    .ready (lmx2594_config_end ), //完成信号
    .sdi_data(lmx2594_rded_data ),
    .sdi (lmx2594_muxout_1 ), //spi输入信号线
    .spi_oe (spi_oe_d ), //输入输出选择
    .sync (sync ), //spi同步信号线
    .sck (sck ), //spi时钟 10M
    .sdo (sdo ) //spi输出信号线
    );
    endmodule


















  • 你好,期待得到你的回复

  • 您好

    收到了,请等待我们的回复。

    由于公共假期,答复会有所延迟,带来不便还请谅解。

  • 好的,感谢您在假期中解决我的问题

  • 团队在假期周末不在办公室。 请期待本周回复。 

  • 好的谢谢,待假期结束回复我

  • 您是否无法正确读取任何书面寄存器或某些特定寄存器? 哪些寄存器未正确读取? 

  • 我读分子,分母的值是正确的,我回读R110,R111,R112以及专用的回读寄存器R107,R108,R109是不正确的

  • 你好,期待得到你的回复

  • 您好

    R107到R112是只读寄存器,读回值与写入值不同是正常现象。

    返回到您的问题,您是否无法锁定它?

    您使用了哪种校准模式?

  • 我并非写入只读寄存器的值,R110-R112是全辅助校准回读的值寄存器,R107-R109我查看数据表是只读寄存器有一个固定值,我只读了这几个寄存器没有写入数据,我是在全辅助校准模式下,回读的值不像是正确值无法通过这个值判断是否锁定,我使用频谱仪判断已锁定

  • 在扫频的时候是自动校准模式QUICK_RECAL_EN=0 VCO_SEL_FORCE=0 VCO_DACISET_FORCE=0 VCO_CAPCTRL_FORCE=0,当把数据扫完后进入全辅助模式QUICK_RECAL_EN=0 VCO_SEL_FORCE=1 VCO_DACISET_FORCE=1 VCO_CAPCTRL_FORCE=1在进行配置R16,R19,R20。但是现在回读值不正确是否跟我配置有关系,希望得到一份规范的配置表

  • 您好

    我们再看一下,请等待我们的回复。

  • 好的谢谢,有进展请您及时回复我

  • 您好,请问有进展了吗