CDC3S04: 使能上拉问题

您好

RESET resets REQ1PRIO/REQ4PRIO and REQ1INT/REQ4INT bits to their default values (CLK1/4 is ON) but does not change the remaining internal SW bits. During RESET, any I 2C operation is blocked until RESET is deactivated. A minimum pulse duration of 500 ns must be applied to activate RESET (the internal glitch-filter suppresses spikes of typical 300 ns).

您是对这部有疑问是吗？根据底下辅助说明，关于复位只是复位默认的状态，在复位中，I2C的相关操作会停止，如果您默认是CLk1和CLK4 是输出，那么您复位过程可以让他直接输出，但是在复位期间不允许任何的I2C操作 。