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AFE58JD32: The problem of odd-even channel changes in the output data of AFE58JD2 in the ramp mode

LI LI
Prodigy 25 points
Part Number: AFE58JD32


Dear TI experts,

We have encountered a problem while using the AFE58JD32 device.

We are using the JESD204B interface of AFE58JD32 (4 lane mode, F=6, K=3)

We set the AFE58JD32 to the ramp mode. Then, the odd channels and even channels differ by 1, and each channel increases by 2 in sequence.（As shown in the figure below）

However, whenever we power on the device again, if we configure the AFE58JD32 to the ramp mode, we will observe the following situation

After this power-on operation, the value of channels0 is an odd number. On the next power-on, the value of channels0 will be an even number. This means that after powering on, the value of channel 0 could be an odd number or an even number.

How should I go about solving this problem?

thank you

  • 0
    TI__Mastermind 28365 points

    已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

  • 0 回复 Eirwen
    Prodigy 25 points

    好的，谢谢TI的专家。

    因为我们使用的AFE58JD32芯片是一个ADC分时复用 采集转换两个模拟通道的数据（这里就涉及到了奇偶采样的时刻），当我们给AFE58JD32的IN1输入正弦波测试信号的时候，经过FPGA解析后，这次上电后，正弦波波形在通道0，下一次上电后，正弦波波形就在通道1，这是随机的。我们想让通道关系固定下来。

    如下图所示

    我们给IN1输入正弦波测试信号，某次上电后，正弦波出现在通道0

    我们给IN1输入正弦波测试信号，某次上电后，正弦波出现在通道1

    这就是我们遇到的情况（我怀疑是奇偶采样时刻没有确定导致的？）

    此外，我们从AFE58JD32数据手册查到了TX_TRIG这个信号：TX_TRIG信号提供了一种机制来确定相对于系统时钟的奇偶输入信号的采样瞬间

    我们尝试使用TX_TRIG信号，但是在运行的时候，没有发现解析后的奇偶通道发生交换。

    期待TI专家的回复！

  • 0 回复 Eirwen
    Prodigy 25 points

    Hi,TI的专家，你们好
    AFE58JD32是NDA器件，涉及了TX_TRIG，需要单独给你们发邮件？

  • 0 回复 LI LI
    TI__Mastermind 28365 points

    可以通过私信发给我（鼠标放在我头像上，有个“发送私信”的选项）

  • 0 回复 Eirwen
    Prodigy 25 points

    Hi,TI专家你好，没有发现那个发送私信的选项((

  • 0 回复 LI LI
    TI__Mastermind 28365 points

    我给您发了私信，您看下页面的右上角应该有提示

  • 0 回复 Eirwen
    TI__Mastermind 28365 points

    Did this issue get resolved after using TX_TRIG to synchronize the ADC channels?

  • 0 回复 Eirwen
    Prodigy 25 points

    I found that the tx_trig signal seems not to be functioning (because during my operation, I triggered the tx_trig signal again, but there was no occurrence of the odd-even channel swap). I tested and discovered that the sysref signal also affects the exchange of odd-even channel data (not the periodic sysref signal). In the running project, by generating the sysref signal again, there is a probability of odd-even channel swap. Why is that?

  • 0 回复 LI LI
    TI__Mastermind 28365 points

    TX_TRIG and SYSREF both signals reset the internal clock divider which determine the sampling of odd and even channel. TX_TRIG and SYSREF frequency has to be multiple of Fs/2. If it is not multiple of Fs/2 then phase alignment for odd and even channel sampling won't happen properly. 

  • 0 回复 Eirwen
    Prodigy 25 points

    Hi,Eirwen
    Thank you for your reply.

    The frequency of sysref depends on the values of linerate, F and K and n.

    Fs=80Mhz, Fs/2 = 40Mhz 

    fBITRATE=4.8Gbps,F=6,K=3 and the n takes integer values.

    The frequency of sysref is with decimals, so there is no value of n that makes Fs/2 and sysref have an integer multiple relationship.
    So, how should we go about solving this?

  • 0 回复 LI LI
    TI__Mastermind 28365 points

    Sysref period should be multiple of 2*LMFC period. Sysref frequency = Fs/(2*K*N), where N is integer and K=3 for user