Part Number: DAC37J82EVM
Other Parts Discussed in Thread: DAC37J82
Hello,
We are evaluating the deterministic latency of a DAC37J82 operating with
a JESD204B Subclass 1 interface. We measure approximately 250 to 260 ns
from an FPGA waveform-change trigger to the observable change at the DAC
analog output. This is significantly longer than we expected from the
known FPGA, GTY, RBD and documented DAC pipeline contributions.
Our current JESD204B configuration is:
- Device: DAC37J82
- Subclass: 1
- L = 4
- M = 2
- F = 1
- S = 1
- K = 32
- N = N' = 16
- DAC sample clock / DACCLK: 983.04 MHz
- JESD lane rate: approximately 9.8304 Gbps
- RBD = 22 frame cycles
- Interpolation disabled
- PAP disabled
- Mixer, QMC and inverse-sinc functions disabled
The FPGA continuously transmits valid JESD204B sample data. The trigger
only changes the generated sample waveform; it does not reset or
reinitialize the JESD link. SYNC remains asserted during the normal
latency measurement.
Our measured latency breakdown is approximately:
1. Trigger to waveform-generator data change:
4.1 ns
2. Trigger to the GTY TX parallel-data interface:
28.5 ns
3. Trigger through a GTY near-end PMA loopback to the GTY RX parallel
interface:
82 to 90 ns
4. Trigger to the DAC analog-output waveform change:
approximately 250 to 260 ns
Changing RBD from 22 to 26 increases the total analog-output latency by
approximately 4 ns. This agrees with four frame periods at 983.04 MHz:
4 / 983.04 MHz = approximately 4.07 ns
Therefore, the RBD setting appears to be active and behaves as expected.
However, the overall trigger-to-analog-output latency remains around
250 ns.
As an additional diagnostic, we tested the SIFDAC path by changing the
SIFDAC data through the serial interface. The approximate response times
were:
- DACCLK = 983.04 MHz: approximately 151 to 153 ns
- DACCLK = 491.52 MHz: approximately 300 ns
The response time approximately doubles when DACCLK is halved, suggesting
that a large portion of this response is determined by a DACCLK-cycle-
based synchronization or digital pipeline.
We also tested the PAP function at 491.52 MHz:
- PAP disabled: approximately 300 ns
- PAP enabled: approximately 440 ns
- Increment: approximately 140 ns
This increment corresponds to approximately 69 DACCLK cycles and is close
to the documented PAP latency of 68 DACCLK cycles. This gives us
confidence that our measurement can identify DACCLK-cycle-based latency
changes.
We understand that the SIFDAC path may include serial-register update and
clock-domain synchronization latency, and that it may not follow exactly
the same path as normal JESD204B sample data. We therefore do not assume
that the measured SIFDAC latency directly represents the JESD receive
latency. We are using it only as a diagnostic indication that a relatively
long clocked path may exist inside the DAC.
Could you please clarify the following points?
1. What is the expected latency from the DAC37J82 JESD serial input to the
analog output for the configuration listed above?
2. Which internal blocks contribute to this latency, and how many DACCLK
or frame-clock cycles does each block contribute?
3. Is there an elastic buffer, JESD receive FIFO, synchronization stage or
common digital pipeline after the SerDes/8b10b block that contributes
significant latency?
4. Can this FIFO or digital pipeline be bypassed or configured for minimum
latency while retaining JESD204B Subclass 1 deterministic latency?
5. Does the documented 11-DACCLK-cycle latency apply to this exact
configuration with interpolation, PAP, mixer, QMC and inverse-sinc
disabled? If so, from which internal reference point to which output
point are those 11 cycles defined?
6. Which internal blocks are shared by the SIFDAC path and the normal
JESD204B sample-data path?
7. Does a SIFDAC response of approximately 150 DACCLK cycles indicate a
normal register-update synchronization delay, or does it indicate the
latency of a shared DAC digital-output pipeline?
8. Is there a recommended register configuration or test method for
measuring the minimum deterministic JESD-input-to-analog-output latency
of the DAC37J82?
Our primary concern is the approximately 250 to 260 ns total
trigger-to-analog-output latency. The SIFDAC measurement is only an
additional observation that may help identify where the unexpected delay
is introduced.
Thank you.
