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ADC的差分输出隔离问题

Other Parts Discussed in Thread: ADS1675, ISO7820

目前,使用了5片ADS1675设计5通道采集,最后连接到FPGA。现在想对ADC输出做隔离,而1675输出由三对差分对,(1)SCLK(2)DOUT
(3)DRDY,

而时钟CLK是32M,三倍以后SCLK就是96M,我想问一下,怎么对这个三对差分线做隔离。

有人推荐用网口变压器做,这种方案可行吗?如果有其他方案,请告诉我一下。万般感谢!