ADS1299使用內部測試訊號沒有訊號

目前我又做了更改，現在START、RESET都試HIGH，CS則為LOW，DIN和DOUT則為一直線的HIGH，SCLK為一直線的LOW，DRDY也為LOW

依照數據表第36頁的圖42來看的話，發現我的SCLK時鐘並沒有工作，導致DIN和DOUT沒有正常波型

void的用途是把每個命令分別宣告為函式，再main中呼叫已宣告的函式。

#include "ti/devices/msp432p4xx/inc/msp.h"
#include <stdint.h>

static uint8_t RXData[];
static uint8_t TXData;
static char i;
#define HZ  3000000UL//3MHZ MCLK


int main(void)
{
////////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////////
    WDT_A->CTL = WDT_A_CTL_PW |             // Stop watchdog timer
            WDT_A_CTL_HOLD;

    P1->SEL0 |= BIT5 | BIT6 | BIT7;         // Set P1.5, P1.6, and P1.7 as
                                            // SPI pins functionality

    //P3->DIR |= BIT0;                        // P3.0 set as output    CS

    EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SWRST; // Put eUSCI state machine in reset
    EUSCI_B0->CTLW0 = EUSCI_B_CTLW0_SWRST | // Remain eUSCI state machine in reset
            EUSCI_B_CTLW0_MST |             // Set as SPI master
            EUSCI_B_CTLW0_SYNC |            // Set as synchronous mode
            EUSCI_B_CTLW0_CKPL_OFS |            // Set clock polarity low
            EUSCI_B_CTLW0_CKPH |            //Phase high
            EUSCI_B_CTLW0_MSB;              // MSB first

    EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SSEL__ACLK; // ACLK
    EUSCI_B0->BRW = 0x01;                   // /2,fBitClock = fBRCLK/(UCBRx+1).
    EUSCI_B0->CTLW0 &= ~EUSCI_B_CTLW0_SWRST;// Initialize USCI state machine
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 

    CS_High();
    ads1299_initial();

    P5->DIR |= BIT1; //PWDN  High
    __delay_cycles(HZ);
    //void RESET();
    void SDATAC();
    __delay_cycles(HZ);
    WREG(0x03 + 0x40,0xE0);//Config3
    WREG(0x01 + 0x40,0x92);//Config1
    WREG(0x02 + 0x40,0xD0);//Config2   0xC0
    WREG(0x05 + 0x40,0x05); //channel1 Normal electrode input  0x60
    P2->DIR |= BIT6; //Set Start High
    //void START();
    __delay_cycles(HZ);
    //WREG(0x17 + 0x40,0x00);//Config4

    void RDATAC();
    //__delay_cycles(HZ);
    //void Testsignal();
    RXData[i] = EUSCI_B0->RXBUF;

}

void spiTx (uint8_t byte)
{
        while(EUSCI_B0->IFG & EUSCI_B_IFG_TXIFG)
        {
            EUSCI_B0->TXBUF = byte;           // Transmit characters
        }
}
void spiRx (void)
{

    RXData[i] = EUSCI_B0->RXBUF;
}
void CS_High (void)
{
    P3->DIR |= BIT0; //CS_High
}
void CS_Low (void)
{
    P3->OUT ^= BIT0; //CS_Low
}
void ads1299_initial (void)
{
    __delay_cycles(5*HZ);
    P2->OUT ^= BIT7;      //RESET Low
    __delay_cycles((4*HZ)/1000000);
    P2->DIR |= BIT7;      //RESET High
    __delay_cycles((20*HZ)/1000000);
    CS_High();
    __delay_cycles(HZ);
}
void RESET(void)
{
    CS_Low();
    spiTx(0x06);
    __delay_cycles((12*HZ)/1000000);
    //__delay_cycles(HZ);
    CS_High();
}
void SDATAC(void)
{
    CS_Low();
    spiTx(0x11);
    CS_High();
    __delay_cycles((3*HZ)/1000000);
}
void WREG(uint8_t _address, uint8_t value)
{
    uint8_t opcode1 = _address + 0x40;
    CS_Low();
    spiTx(opcode1);
    spiTx(0x00);
    spiTx(value);
    CS_High();
}
uint8_t RREG(uint8_t _address)//在RDATAC模式下，RREG指令會被忽略(datasheet P35)
{
    uint8_t opcode1 = _address + 0x20;
    CS_Low();
    spiTx(opcode1);
    spiTx(0x00);
    //uint8_t abv[] = spiRx(_address);
    CS_High();
}
void RDATAC(void)
{
    CS_Low();
    spiTx(0x10);
    CS_High();
    __delay_cycles((3*HZ)/1000000);
}
void START(void)
{
    CS_Low();
    spiTx(0x08);
    CS_High();
}

void Testsignal(void)
{
    void SDATAC();
    __delay_cycles(HZ);
    WREG(0x02 + 0x40,0xD0);
    WREG(0x05 + 0x40,0x05);
    void RDATAC();
}