DLP2021-Q1: Interrupt & HOST_IRQ

参考中断和处理：

while(1)
{
if(isHostMuted() == false)
{
enableSPIPins();
if(isfpgainterrupt)
{
isfpgainterrupt = false;
uint32_t interrupts;
bool success = false;
//interrupt register read must have valid checksum
while(!success)
{
success = spiread(FPGA_ADDR_INTSET, &interrupts);
}
spiwrite(FPGA_ADDR_INTCLR, interrupts); //Clear interrupts that are set so host irq goes low
if(interrupts & INT_INIT_DONE)
{
__delay_cycles(800000); //50ms delay
fpgaInitTemp();
initTimer();
//if(!eeprom_data_valid)
//{
redpwm = RED_DEFAULT_PWM & 0x3FF;
greenpwm = GREEN_DEFAULT_PWM & 0x3FF;
bluepwm = BLUE_DEFAULT_PWM & 0x3FF;
//}
enableFPGAInterupts(INT_BROWNOUT | INT_LOOP_COMP);
fpgaStopVideo(); //Must stop video prior to trying to access flash via registers
getVideoCount(&videoCount);
getAllVideoInfo(videos, videoCount);
fpgaSetFramerate(VIDEO_FRAMERATE);
// If there is a video in flash play the first video found, if not then load the first image found
for(uint8_t i = 0; i < videoCount; i++){
if(videos[i].frameCount > 1){
fpgaSetVideo1(videos[i].address, VIDEO1_1_LOOPS, videos[i].frameCount);
fpgaSetVideo2(videos[i].address, VIDEO1_2_LOOPS, videos[i].frameCount);
break;
}
else{
fpgaSetVideo1(videos[0].address, VIDEO1_1_LOOPS, videos[0].frameCount);
fpgaSetVideo2(videos[0].address, VIDEO1_2_LOOPS, videos[0].frameCount);
}
}
fpgaPlayVideo(VIDEO_AUTOSTOP, 0, VIDEO_LOOPCONFIGS, VIDEO_TOGGLECONFIGS);

}
if(interrupts & INT_BROWNOUT)
{
//delay 1ms to give time to complete DMD park
__delay_cycles(PARK_DELAY1);
disableFPGAPower();
}
if(interrupts & INT_VID_COMP)
{
//Do something when each video is complete
}
if(interrupts & INT_LOOP_COMP)
{
//Do something when each video loop is complete
}
}
if(istimerinterrupt)
{
istimerinterrupt = false;
int16_t dmdtemp;
fpgaReadDMDTemp(&dmdtemp);
checkParkDMD(dmdtemp);
}
if(isuartinterrupt)
{
isuartinterrupt = false;
uartProcessByte();
}