DS90UB983-Q1: 使用UB984打pattern屏幕未出图，查看0xE8、0xE9、0xEA等寄存器发现没有training，但是硬件上HPD是高的。请问984有相关的寄存器可以改变HPD的状态，强行training吗

Ryan yan

Prodigy 40 points

Part Number: DS90UB983-Q1
Other Parts Discussed in Thread: DS90UB984-Q1

加串器使用UB983，解串器使用UB984，使用DP1进行输出，但发现硬件设计错误，现在把eDP1_HPD的86引脚飞线到R36，但984打pattern仍不出图

8 天前

0 Links 8 天前

TI__Mastermind 36500 points

您好，

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

0 Ryan yan 6 天前

Prodigy 40 points

您好，现在解串器984打pattern，屏幕出图了，但是用983打pattern未出图，我们加串器983硬件上配置的是 FPD-LINK4 INDEPENDENT但是由于我们只连接了一个屏，因此在生成配置文件时使用的是Single port 0，这是否会有影响，图是983的MODEL_SEL配置

0 Links 6 天前回复 Ryan yan

TI__Mastermind 36500 points

这里有几个问题：
系统层面问题：
一级供应商/原始设备制造商？
新的设计还是生产系统？
串行器/解串器部件编号？
FPD-Link III 或 IV 模式？
分辨率、色彩深度、PCLK 频率？
FPD-Link 模式/FPD 速率？
DPRX/DPTX 速率？
系统芯片/源设备？
已构建的系统数量与故障设备数量之比？
单个或多个显示器/主机/电子控制单元/车辆控制单元系统？

故障模式详情：
观察到的问题（黑屏/闪烁/无锁定/失真/间歇性出现）？
问题发生的时间：启动时/运行时等？
重现频率？
环境：车辆/测试台？
恢复方法：自动/软重启/硬重启/电源重启/重新初始化？
温度依赖性：室温/低温/高温？

关于故障模式：
你能说明一下你的设置情况吗？也就是说，983 与 984 相连，但你却试图将数据输出到本地的“patgen”设备上？
问题在于，您看到的是 984 个链接训练失败的情况？

您是否已正确将视频流映射到 DP1 了？
您在此处设置的是什么 DPTX 速率和通道数量？
能否发送您的脚本以便审核？

请使用以下脚本来记录故障模式发生时的情况。

全屏 7318.ALP_Ux98x_SERDES_Full_Diagnostics_V1 (1).txt 下载

## TI Confidential - NDA Restrictions
##
## Copyright 2018 Texas Instruments Incorporated. All rights reserved.
##
## IMPORTANT: Your use of this Software is limited to those specific rights
## granted under the terms of a software license agreement between the user who
## downloaded the software, his/her employer (which must be your employer) and
## Texas Instruments Incorporated (the License). You may not use this Software
## unless you agree to abide by the terms of the License. The License limits your
## use, and you acknowledge, that the Software may not be modified, copied or
## distributed unless embedded on a Texas Instruments microcontroller which is
## integrated into your product. Other than for the foregoing purpose, you may
## not use, reproduce, copy, prepare derivative works of, modify, distribute,
## perform, display or sell this Software and/or its documentation for any
## purpose.
##
## YOU FURTHER ACKNOWLEDGE AND AGREE THAT THE SOFTWARE AND DOCUMENTATION ARE
## PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
## INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY, TITLE,
## NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TEXAS
## INSTRUMENTS OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER CONTRACT,
## NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR OTHER LEGAL
## EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES INCLUDING BUT NOT
## LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL
## DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS,
## TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT
## LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
##
## Should you have any questions regarding your right to use this Software,
## contact Texas Instruments Incorporated at www.TI.com.
## Debug Script Version 1
import time

#######################User_Input############################
serAddr = 0x18
desAlias0 = 0x58
SER = "Ux983"  # Chosse HH983 or Ux983 or Ux943A or Ux981 or Ux94x
DES = "Ux984"  # Chosse HH984 or Ux984 or Ux988 or Ux948
MST = 0        # For Ux983 Select 0 for SST and 1 for MST mode
DP0 = 1        # For Ux984 Enable DPTX port0 diagnostics
DP1 = 0        # For Ux984 Enable DPTX port1 diagnostics

##################Keep Always ON#############################
VP = 1  # Enable VP diagnostics
SER_MSAs = 1  # Dump 983 SER MSAs
DTGs = 1  # dump DES DTGs
DPRX = 1  # Enable 983 DPRX diagnostics
DPTX = 1  # Enable 984 DPTX diagnostics
#############################################################

def apb_read_reg(DevAddrRxMain, addr16b):
    APB_CTL = 0x48
    APB_AUTO_INC = {'pos': 2, 'wid': 1}
    APB_READ = {'pos': 1, 'wid': 1}
    APB_ENABLE = {'pos': 0, 'wid': 1}
    APB_ADR0 = 0x49
    APB_ADR1 = 0x4A
    APB_DATA0 = 0x4B
    APB_DATA1 = 0x4C
    APB_DATA2 = 0x4D
    APB_DATA3 = 0x4E
    addr16b_lsb = addr16b & 0xFF
    addr16b_msb = (addr16b & 0xFF00) >> 8
    board.WriteI2C(DevAddrRxMain, APB_ADR0, addr16b_lsb)
    board.WriteI2C(DevAddrRxMain, APB_ADR1, addr16b_msb)
    board.WriteI2C(DevAddrRxMain, APB_CTL, 0x03)
    apbData0 = board.ReadI2C(DevAddrRxMain, APB_DATA0)
    apbData1 = board.ReadI2C(DevAddrRxMain, APB_DATA1)
    apbData2 = board.ReadI2C(DevAddrRxMain, APB_DATA2)
    apbData3 = board.ReadI2C(DevAddrRxMain, APB_DATA3)
    apbData = (apbData3 << 24) | (apbData2 << 16) | (apbData1 << 8) | (apbData0 << 0)
    val32bit = apbData
    return val32bit


def apb_write_reg(DevAddrRxMain, addr16b, data32b):
    APB_CTL = 0x48
    APB_AUTO_INC = {'pos': 2, 'wid': 1}
    APB_READ = {'pos': 1, 'wid': 1}
    APB_ENABLE = {'pos': 0, 'wid': 1}
    APB_ADR0 = 0x49
    APB_ADR1 = 0x4A
    APB_DATA0 = 0x4B
    APB_DATA1 = 0x4C
    APB_DATA2 = 0x4D
    APB_DATA3 = 0x4E
    addr16b_lsb = addr16b & 0xFF
    addr16b_msb = (addr16b & 0xFF00) >> 8
    board.WriteI2C(DevAddrRxMain, APB_ADR0, addr16b_lsb)
    board.WriteI2C(DevAddrRxMain, APB_ADR1, addr16b_msb)
    # print 'data32b', data32b
    apbData0 = int((data32b & 0x000000FF) >> 0)
    # print 'type', type(apbData0), apbData0
    apbData1 = int((data32b & 0x0000FF00) >> 8)
    apbData2 = int((data32b & 0x00FF0000) >> 16)
    apbData3 = int((data32b & 0xFF000000) >> 24)
    board.WriteI2C(DevAddrRxMain, APB_DATA0, apbData0)
    board.WriteI2C(DevAddrRxMain, APB_DATA1, apbData1)
    board.WriteI2C(DevAddrRxMain, APB_DATA2, apbData2)
    board.WriteI2C(DevAddrRxMain, APB_DATA3, apbData3)
    board.WriteI2C(DevAddrRxMain, APB_CTL, 0x01)


def MSA_apb_read_reg(addr16b, channel, Device_ID):
    APB_CTL = 0x48
    APB_AUTO_INC = {'pos': 2, 'wid': 1}
    APB_READ = {'pos': 1, 'wid': 1}
    APB_ENABLE = {'pos': 0, 'wid': 1}
    APB_ADR0 = 0x49
    APB_ADR1 = 0x4A
    APB_DATA0 = 0x4B
    APB_DATA1 = 0x4C
    APB_DATA2 = 0x4D
    APB_DATA3 = 0x4E

    if channel == 0:
        page = 0x03
    elif channel == 1:
        page = 0x0B
    else:
        page = 0x03

    addr16b_lsb = addr16b & 0xFF
    addr16b_msb = (addr16b & 0xFF00) >> 8

    board.WriteI2C(Device_ID, APB_ADR0, addr16b_lsb)

    board.WriteI2C(Device_ID, APB_ADR1, addr16b_msb)

    board.WriteI2C(Device_ID, APB_CTL, page)

    apbData0 = board.ReadI2C(Device_ID, APB_DATA0)

    apbData1 = board.ReadI2C(Device_ID, APB_DATA1)

    apbData2 = board.ReadI2C(Device_ID, APB_DATA2)

    apbData3 = board.ReadI2C(Device_ID, APB_DATA3)

    apbData = (apbData3 << 24) + (apbData2 << 16) + (apbData1 << 8) + (apbData0 << 0)
    val32bit = apbData

    return val32bit


def Measure_Video_DPTX(desAlias0, Port, PRNT_STATUS):
    print("")
    Offset = 0x00

    htotal = MSA_apb_read_reg(0x180 + Offset, int(Port), desAlias0)

    vtotal = MSA_apb_read_reg(0x184 + Offset, int(Port), desAlias0)

    hres = MSA_apb_read_reg(0x194 + Offset, int(Port), desAlias0)

    vres = MSA_apb_read_reg(0x198 + Offset, int(Port), desAlias0)

    hstart = MSA_apb_read_reg(0x19C + Offset, int(Port), desAlias0)

    vstart = MSA_apb_read_reg(0x1A0 + Offset, int(Port), desAlias0)

    hswidth = MSA_apb_read_reg(0x18C + Offset, int(Port), desAlias0)

    vswidth = MSA_apb_read_reg(0x190 + Offset, int(Port), desAlias0)

    if PRNT_STATUS == 1:
        print("Port", Port, ": DPTX VIDEO RESOLUTION:")
        print("Port", Port, ": htotal (0x180) = " + str(htotal))
        print("Port", Port, ": vtotal (0x184) = " + str(vtotal))
        print("Port", Port, ": hres (0x18C) = " + str(hres))
        print("Port", Port, ": vres (0x190) = " + str(vres))
        print("Port", Port, ": hstart (0x19C) = " + str(hstart))
        print("Port", Port, ": vstart (0x1A0) = " + str(vstart))
        print("Port", Port, ": hswidth (0x18C) = " + str(hswidth))
        print("Port", Port, ": vswidth (0x18C) = " + str(vswidth))

    return htotal, hres, vtotal, vres

def Measure_Video_DPTX_HH(desAlias0, Port, PRNT_STATUS):
        print("")
        Offset = 0x00

        htotal = MSA_apb_read_reg(0x820 + Offset, int(Port), desAlias0)

        vtotal = MSA_apb_read_reg(0x824 + Offset, int(Port), desAlias0)

        hres = MSA_apb_read_reg(0x834 + Offset, int(Port), desAlias0)

        vres = MSA_apb_read_reg(0x838 + Offset, int(Port), desAlias0)

        hstart = MSA_apb_read_reg(0x83C + Offset, int(Port), desAlias0)

        vstart = MSA_apb_read_reg(0x840 + Offset, int(Port), desAlias0)

        hswidth = MSA_apb_read_reg(0x82C + Offset, int(Port), desAlias0)

        vswidth = MSA_apb_read_reg(0x830 + Offset, int(Port), desAlias0)

        if PRNT_STATUS == 1:
            print("Port", Port, ": DPTX VIDEO RESOLUTION:")
            print("Port", Port, ": htotal (0x820) = " + str(htotal))
            print("Port", Port, ": vtotal (0x824) = " + str(vtotal))
            print("Port", Port, ": hres (0x834) = " + str(hres))
            print("Port", Port, ": vres (0x838) = " + str(vres))
            print("Port", Port, ": hstart (0x83C) = " + str(hstart))
            print("Port", Port, ": vstart (0x840) = " + str(vstart))
            print("Port", Port, ": hswidth (0x82C) = " + str(hswidth))
            print("Port", Port, ": vswidth (0x830) = " + str(vswidth))

        return htotal, hres, vtotal, vres

def apb_read_reg_984_DPTX(addr16b, channel, Device_ID):
	APB_CTL = 0x48
	APB_AUTO_INC = {'pos': 2, 'wid': 1}
	APB_READ = {'pos': 1, 'wid': 1}
	APB_ENABLE = {'pos': 0, 'wid': 1}
	APB_ADR0 = 0x49
	APB_ADR1 = 0x4A
	APB_DATA0 = 0x4B
	APB_DATA1 = 0x4C
	APB_DATA2 = 0x4D
	APB_DATA3 = 0x4E

	if channel == 0:
		page = 0x03
	elif channel == 1:
		page = 0x0B
	else:
		page = 0x03

	addr16b_lsb = addr16b & 0xFF
	addr16b_msb = (addr16b & 0xFF00) >> 8
	##print 'READ inst'
	board.WriteI2C(Device_ID, APB_ADR0, addr16b_lsb)
	board.WriteI2C(Device_ID, APB_ADR1, addr16b_msb)
	board.WriteI2C(Device_ID, APB_CTL, page)
	apbData0 = board.ReadI2C(Device_ID, APB_DATA0)
	apbData1 = board.ReadI2C(Device_ID, APB_DATA1)
	apbData2 = board.ReadI2C(Device_ID, APB_DATA2)
	apbData3 = board.ReadI2C(Device_ID, APB_DATA3)
	apbData = (apbData3 << 24) + (apbData2 << 16) + (apbData1 << 8) + (apbData0 << 0)
	val32bit = apbData
	Device_ID = 0x00
	return val32bit

def Ux984_APB_Dump(Port,Device_RX):
	Stream = 0 # 0, 1, 2, or 3
	if Stream == 0 :
		Offset = 0x00
	elif Stream == 1:
		Offset = 0x400
	elif Stream == 2:
		Offset = 0x420
	elif Stream == 3:
		Offset = 0x500
	else:
		Offset = 0x00
	print "PORT ",Port," DPTX APB Dump: Main Stream Attributes"

	REG_000= apb_read_reg_984_DPTX(0x000,int(Port), Device_RX )
	print "REG_000 (LINK_BW_SET) = ", (REG_000)

	REG_004= apb_read_reg_984_DPTX(0x004,int(Port), Device_RX )
	print "REG_004 (LANE_COUNT_SET) = ", (REG_004)

	REG_008= apb_read_reg_984_DPTX(0x008,int(Port), Device_RX )
	print "REG_008 (ENHANCED_FRAME_EN) = ", (REG_008)

	REG_00C= apb_read_reg_984_DPTX(0x00C,int(Port), Device_RX )
	print "REG_00C (TRAINING_PATTERN_SET) = ", (REG_00C)

	REG_010= apb_read_reg_984_DPTX(0x010,int(Port), Device_RX )
	print "REG_010 (LINK_QUAL_PATTERN_SET) = ", (REG_010)

	REG_014= apb_read_reg_984_DPTX(0x014,int(Port), Device_RX )
	print "REG_014 (SCRAMBLING_DISABLE) = ", (REG_014)

	REG_018= apb_read_reg_984_DPTX(0x018,int(Port), Device_RX )
	print "REG_018 (DOWNSPREAD_CTRL) = ", (REG_018)

	REG_01C= apb_read_reg_984_DPTX(0x01C,int(Port), Device_RX )
	print "REG_01C (EDP_CAPABILITY_CONFIG) = ", (REG_01C)

	REG_020= apb_read_reg_984_DPTX(0x020,int(Port), Device_RX )
	print "REG_020 (HBR2_COMPLIANCE_SCRAMBLER_RESET) = ", (REG_020)

	REG_024= apb_read_reg_984_DPTX(0x024,int(Port), Device_RX )
	print "REG_024 (DISPLAYPORT_VERSION) = ", (REG_024)

	REG_028= apb_read_reg_984_DPTX(0x028,int(Port), Device_RX )
	print "REG_024 (PHY_POWER_STATE) = ", (REG_028)

	REG_02C= apb_read_reg_984_DPTX(0x02C,int(Port), Device_RX )
	print "REG_02C (LANE_REMAP_CONTROL) = ", (REG_02C)

	REG_030= apb_read_reg_984_DPTX(0x030,int(Port), Device_RX )
	print "REG_030 (CUSTOM_80BIT_PATTERN_0) = ", (REG_030)

	REG_034= apb_read_reg_984_DPTX(0x034,int(Port), Device_RX )
	print "REG_034 (CUSTOM_80BIT_PATTERN_1) = ", (REG_034)

	REG_038= apb_read_reg_984_DPTX(0x038,int(Port), Device_RX )
	print "REG_038 (CUSTOM_80BIT_PATTERN_2) = ", (REG_038)

	REG_060= apb_read_reg_984_DPTX(0x060,int(Port), Device_RX )
	print "REG_060 (FEC_ENABLE) = ", (REG_060)

	REG_080= apb_read_reg_984_DPTX(0x080,int(Port), Device_RX )
	print "REG_080 (TRANSMITTER_OUTPUT_ENABLE) = ", (REG_080)

	REG_084= apb_read_reg_984_DPTX(0x084,int(Port), Device_RX )
	print "REG_084 (VIDEO_STREAM_ENABLE) = ", (REG_084)

	REG_088= apb_read_reg_984_DPTX(0x088,int(Port), Device_RX )
	print "REG_088 (SECONDARY_STREAM_ENABLE) = ", (REG_088)

	REG_08C= apb_read_reg_984_DPTX(0x08C,int(Port), Device_RX )
	print "REG_088 (SECONDARY_DATA_WINDOW) = ", (REG_08C)

	REG_090= apb_read_reg_984_DPTX(0x090,int(Port), Device_RX )
	print "REG_090 (SOFT_RESET) = ", (REG_090)

	REG_094= apb_read_reg_984_DPTX(0x094,int(Port), Device_RX )
	print "REG_094 (INPUT_SOURCE_ENABLE) = ", (REG_094)

	REG_098= apb_read_reg_984_DPTX(0x098,int(Port), Device_RX )
	print "REG_098 (FEC_ENABLE) = ", (REG_098)

	REG_0C0= apb_read_reg_984_DPTX(0x0C0,int(Port), Device_RX )
	print "REG_0C0 (ORCE_SCRAMBLER_RESET) = ", (REG_0C0)

	REG_0C4= apb_read_reg_984_DPTX(0x0C4,int(Port), Device_RX )
	print "REG_0C4 (USER_CONTROL_STATUS) = ", (REG_0C4)

	REG_0C8= apb_read_reg_984_DPTX(0x0C8,int(Port), Device_RX )
	print "REG_0C8 (USER_DATA_CONTROL) = ", (REG_0C8)

	REG_0F8= apb_read_reg_984_DPTX(0x0F8,int(Port), Device_RX )
	print "REG_0F8 (CORE_CAPABILITIES) = ", (REG_0F8)

	REG_0FC= apb_read_reg_984_DPTX(0x0FC,int(Port), Device_RX )
	print "REG_0FC (CORE_ID) = ", (REG_0FC)

	REG_100= apb_read_reg_984_DPTX(0x100,int(Port), Device_RX )
	print "REG_100 (AUX_COMMAND) = ", (REG_100)

	REG_104= apb_read_reg_984_DPTX(0x104,int(Port), Device_RX )
	print "REG_104 (AUX_WRITE_FIFO) = ", (REG_104)

	REG_108= apb_read_reg_984_DPTX(0x108,int(Port), Device_RX )
	print "REG_108 (AUX_ADDRESS) = ", (REG_108)

	REG_10C= apb_read_reg_984_DPTX(0x10C,int(Port), Device_RX )
	print "REG_10C (AUX_CLOCK_DIVIDER) = ", (REG_10C)

	REG_110= apb_read_reg_984_DPTX(0x110,int(Port), Device_RX )
	print "REG_110 (AUX_REPLY_TIMEOUT_INTERVAL) = ", (REG_110)

	REG_128= apb_read_reg_984_DPTX(0x128,int(Port), Device_RX )
	print "REG_128 (SINK_HPD_STATE) = ", (REG_128)

	REG_130= apb_read_reg_984_DPTX(0x130,int(Port), Device_RX )
	print "REG_130 (INTERRUPT_STATE) = ", (REG_130)

	REG_134= apb_read_reg_984_DPTX(0x134,int(Port), Device_RX )
	print "REG_134 (AUX_REPLY_DATA) = ", (REG_134)

	REG_138= apb_read_reg_984_DPTX(0x138,int(Port), Device_RX )
	print "REG_138 (AUX_REPLY_CODE) = ", (REG_138)

	REG_13C= apb_read_reg_984_DPTX(0x13C,int(Port), Device_RX )
	print "REG_13C (AUX_REPLY_COUNT) = ", (REG_13C)

	REG_140= apb_read_reg_984_DPTX(0x140,int(Port), Device_RX )
	print "REG_140 (INTERRUPT_STATUS) = ", (REG_140)

	REG_144= apb_read_reg_984_DPTX(0x144,int(Port), Device_RX )
	print "REG_144 (INTERRUPT_MASK) = ", (REG_144)

	REG_148= apb_read_reg_984_DPTX(0x148,int(Port), Device_RX )
	print "REG_148 (REPLY_DATA_COUNT) = ", (REG_148)

	REG_14C= apb_read_reg_984_DPTX(0x14C,int(Port), Device_RX )
	print "REG_14C (AUX_STATUS) = ", (REG_14C)

	REG_150= apb_read_reg_984_DPTX(0x150,int(Port), Device_RX )
	print "REG_150 (AUX_REPLY_CLOCK_WIDTH) = ", (REG_150)

	REG_154= apb_read_reg_984_DPTX(0x154,int(Port), Device_RX )
	print "REG_154 (AUX_WAKE_ACK_DETECTED) = ", (REG_154)

	REG_158= apb_read_reg_984_DPTX(0x158,int(Port), Device_RX )
	print "REG_158 (GP_HOST_TIMER) = ", (REG_158)

	print ""
	print "STREAM: ", Stream, " Register Read: "
	print ""

	REG_0180= apb_read_reg_984_DPTX(0x180+Offset,int(Port), Device_RX )
	print "REG_0180 (MAIN_STREAM_HTOTAL) = ", (REG_0180)

	REG_0184= apb_read_reg_984_DPTX(0x184+Offset,int(Port), Device_RX )
	print "REG_0184 (MAIN_STREAM_VTOTAL) = ", (REG_0184)

	REG_0188= apb_read_reg_984_DPTX(0x188+Offset,int(Port), Device_RX )
	print "REG_0188 (MAIN_STREAM_POLARITY) = ", (REG_0188)

	REG_018C= apb_read_reg_984_DPTX(0x18C+Offset,int(Port), Device_RX )
	print "REG_018C (MAIN_STREAM_HSWIDTH) = ", (REG_018C)

	REG_0190= apb_read_reg_984_DPTX(0x190+Offset,int(Port), Device_RX )
	print "REG_0190 (MAIN_STREAM_VSWIDTH) = ", (REG_0190)

	REG_0194= apb_read_reg_984_DPTX(0x194+Offset,int(Port), Device_RX )
	print "REG_0194 (MAIN_STREAM_HRES) = ", (REG_0194)

	REG_0198= apb_read_reg_984_DPTX(0x198+Offset,int(Port), Device_RX )
	print "REG_0198 (MAIN_STREAM_VRES) = ", (REG_0198)

	REG_019C= apb_read_reg_984_DPTX(0x19C+Offset,int(Port), Device_RX )
	print "REG_019C (MAIN_STREAM_HSTART) = ", (REG_019C)

	REG_01A0= apb_read_reg_984_DPTX(0x1A0+Offset,int(Port), Device_RX )
	print "REG_01A0 (MAIN_STREAM_VSTART) = ", (REG_01A0)

	REG_01A4= apb_read_reg_984_DPTX(0x1A4+Offset,int(Port), Device_RX )
	print "REG_01A4 (MAIN_STREAM_MISC0) = ", (REG_01A4)

	REG_01A8= apb_read_reg_984_DPTX(0x1A8+Offset,int(Port), Device_RX )
	print "REG_01A8 (MAIN_STREAM_MISC1) = ", (REG_01A8)

	REG_01AC= apb_read_reg_984_DPTX(0x1AC+Offset,int(Port), Device_RX )
	print "REG_01AC (MVID) = ", (REG_01AC)

	REG_01B0= apb_read_reg_984_DPTX(0x1B0+Offset,int(Port), Device_RX )
	print "REG_01B0 (TRANSFER_UNIT_CONFIG_SRC_0) = ", (REG_01B0)

	REG_01B4= apb_read_reg_984_DPTX(0x1B4+Offset,int(Port), Device_RX )
	print "REG_01B4 (NVID) = ", (REG_01B4)

	REG_01B8= apb_read_reg_984_DPTX(0x1B8+Offset,int(Port), Device_RX )
	print "REG_01B8 (USER_PIXEL_COUNT) = ", (REG_01B8)

	REG_01BC= apb_read_reg_984_DPTX(0x1BC+Offset,int(Port), Device_RX )
	print "REG_01BC (USER_DATA_COUNT) = ", (REG_01BC)

	REG_01C0= apb_read_reg_984_DPTX(0x1C0+Offset,int(Port), Device_RX )
	print "REG_01C0 (MAIN_STREAM_INTERLACED) = ", (REG_01C0)

	REG_01C4= apb_read_reg_984_DPTX(0x1C4+Offset,int(Port), Device_RX )
	print "REG_01C4 (USER_SYNC_POLARITY) = ", (REG_01C4)

	REG_01C8= apb_read_reg_984_DPTX(0x1C8+Offset,int(Port), Device_RX )
	print "REG_01C8 (USER_CONTROL) = ", (REG_01C8)

	REG_01CC= apb_read_reg_984_DPTX(0x1CC+Offset,int(Port), Device_RX )
	print "REG_01CC (USER_CONTROL) = ", (REG_01CC)

	REG_0500= apb_read_reg_984_DPTX(0x500,int(Port), Device_RX )
	print "REG_0500 (MST_ENABLE) = ", (REG_0500)

	REG_0504= apb_read_reg_984_DPTX(0x504,int(Port), Device_RX )
	print "REG_0504 (MST_PID_TABLE_INDEX) = ", (REG_0504)

	REG_0508= apb_read_reg_984_DPTX(0x504,int(Port), Device_RX )
	print "REG_0508 (MST_PID_TABLE_ENTRY) = ", (REG_0508)

	REG_050C= apb_read_reg_984_DPTX(0x50C,int(Port), Device_RX )
	print "REG_050C (SST_SOURCE_SELECT) = ", (REG_050C)

	REG_0510= apb_read_reg_984_DPTX(0x510,int(Port), Device_RX )
	print "REG_0510 (MST_ALLOCATION_TRIGGER) = ", (REG_0510)

	REG_0514= apb_read_reg_984_DPTX(0x514,int(Port), Device_RX )
	print "REG_0514 (MST_PID_TABLE_SELECT) = ", (REG_0514)

	REG_0518= apb_read_reg_984_DPTX(0x518,int(Port), Device_RX )
	print "REG_0518 (MST_ACTIVE_PAYLOAD_TABLE) = ", (REG_0518)

	REG_0520= apb_read_reg_984_DPTX(0x520,int(Port), Device_RX )
	print "REG_0520 (MST_ACTIVE) = ", (REG_0520)

	REG_0524= apb_read_reg_984_DPTX(0x524,int(Port), Device_RX )
	print "REG_0524 (MST_LINK_FRAME_COUNT) = ", (REG_0524)

	REG_0528= apb_read_reg_984_DPTX(0x528,int(Port), Device_RX )
	print "REG_0528 (MSO_CONFIGURATION) = ", (REG_0528)

	REG_0528= apb_read_reg_984_DPTX(0x528,int(Port), Device_RX )
	print "REG_0528 (MSO_CONFIGURATION) = ", (REG_0528)

	# Port = 1

	# print ""
	# print "PORT ",Port," DPTX APB Dump: Main Stream Attributes"
	# print ""

	# REG_000= apb_read_reg(0x000,int(Port), Device_RX )
	# print "REG_000 (LINK_BW_SET) = ", (REG_000)

	# REG_004= apb_read_reg(0x004,int(Port), Device_RX )
	# print "REG_004 (LANE_COUNT_SET) = ", (REG_004)

	# REG_008= apb_read_reg(0x008,int(Port), Device_RX )
	# print "REG_008 (ENHANCED_FRAME_EN) = ", (REG_008)

	# REG_00C= apb_read_reg(0x00C,int(Port), Device_RX )
	# print "REG_00C (TRAINING_PATTERN_SET) = ", (REG_00C)

	# REG_010= apb_read_reg(0x010,int(Port), Device_RX )
	# print "REG_010 (LINK_QUAL_PATTERN_SET) = ", (REG_010)

	# REG_014= apb_read_reg(0x014,int(Port), Device_RX )
	# print "REG_014 (SCRAMBLING_DISABLE) = ", (REG_014)

	# REG_018= apb_read_reg(0x018,int(Port), Device_RX )
	# print "REG_018 (DOWNSPREAD_CTRL) = ", (REG_018)

	# REG_01C= apb_read_reg(0x01C,int(Port), Device_RX )
	# print "REG_01C (EDP_CAPABILITY_CONFIG) = ", (REG_01C)

	# REG_020= apb_read_reg(0x020,int(Port), Device_RX )
	# print "REG_020 (HBR2_COMPLIANCE_SCRAMBLER_RESET) = ", (REG_020)

	# REG_024= apb_read_reg(0x024,int(Port), Device_RX )
	# print "REG_024 (DISPLAYPORT_VERSION) = ", (REG_024)

	# REG_028= apb_read_reg(0x028,int(Port), Device_RX )
	# print "REG_024 (PHY_POWER_STATE) = ", (REG_028)

	# REG_02C= apb_read_reg(0x02C,int(Port), Device_RX )
	# print "REG_02C (LANE_REMAP_CONTROL) = ", (REG_02C)

	# REG_030= apb_read_reg(0x030,int(Port), Device_RX )
	# print "REG_030 (CUSTOM_80BIT_PATTERN_0) = ", (REG_030)

	# REG_034= apb_read_reg(0x034,int(Port), Device_RX )
	# print "REG_034 (CUSTOM_80BIT_PATTERN_1) = ", (REG_034)

	# REG_038= apb_read_reg(0x038,int(Port), Device_RX )
	# print "REG_038 (CUSTOM_80BIT_PATTERN_2) = ", (REG_038)

	# REG_060= apb_read_reg(0x060,int(Port), Device_RX )
	# print "REG_060 (FEC_ENABLE) = ", (REG_060)

	# REG_080= apb_read_reg(0x080,int(Port), Device_RX )
	# print "REG_080 (TRANSMITTER_OUTPUT_ENABLE) = ", (REG_080)

	# REG_084= apb_read_reg(0x084,int(Port), Device_RX )
	# print "REG_084 (VIDEO_STREAM_ENABLE) = ", (REG_084)

	# REG_088= apb_read_reg(0x088,int(Port), Device_RX )
	# print "REG_088 (SECONDARY_STREAM_ENABLE) = ", (REG_088)

	# REG_08C= apb_read_reg(0x08C,int(Port), Device_RX )
	# print "REG_088 (SECONDARY_DATA_WINDOW) = ", (REG_08C)

	# REG_090= apb_read_reg(0x090,int(Port), Device_RX )
	# print "REG_090 (SOFT_RESET) = ", (REG_090)

	# REG_094= apb_read_reg(0x094,int(Port), Device_RX )
	# print "REG_094 (INPUT_SOURCE_ENABLE) = ", (REG_094)

	# REG_098= apb_read_reg(0x098,int(Port), Device_RX )
	# print "REG_098 (FEC_ENABLE) = ", (REG_098)

	# REG_0C0= apb_read_reg(0x0C0,int(Port), Device_RX )
	# print "REG_0C0 (ORCE_SCRAMBLER_RESET) = ", (REG_0C0)

	# REG_0C4= apb_read_reg(0x0C4,int(Port), Device_RX )
	# print "REG_0C4 (USER_CONTROL_STATUS) = ", (REG_0C4)

	# REG_0C8= apb_read_reg(0x0C8,int(Port), Device_RX )
	# print "REG_0C8 (USER_DATA_CONTROL) = ", (REG_0C8)

	# REG_0F8= apb_read_reg(0x0F8,int(Port), Device_RX )
	# print "REG_0F8 (CORE_CAPABILITIES) = ", (REG_0F8)

	# REG_0FC= apb_read_reg(0x0FC,int(Port), Device_RX )
	# print "REG_0FC (CORE_ID) = ", (REG_0FC)

	# REG_100= apb_read_reg(0x100,int(Port), Device_RX )
	# print "REG_100 (AUX_COMMAND) = ", (REG_100)

	# REG_104= apb_read_reg(0x104,int(Port), Device_RX )
	# print "REG_104 (AUX_WRITE_FIFO) = ", (REG_104)

	# REG_108= apb_read_reg(0x108,int(Port), Device_RX )
	# print "REG_108 (AUX_ADDRESS) = ", (REG_108)

	# REG_10C= apb_read_reg(0x10C,int(Port), Device_RX )
	# print "REG_10C (AUX_CLOCK_DIVIDER) = ", (REG_10C)

	# REG_110= apb_read_reg(0x110,int(Port), Device_RX )
	# print "REG_110 (AUX_REPLY_TIMEOUT_INTERVAL) = ", (REG_110)

	# REG_128= apb_read_reg(0x128,int(Port), Device_RX )
	# print "REG_128 (SINK_HPD_STATE) = ", (REG_128)

	# REG_130= apb_read_reg(0x130,int(Port), Device_RX )
	# print "REG_130 (INTERRUPT_STATE) = ", (REG_130)

	# REG_134= apb_read_reg(0x134,int(Port), Device_RX )
	# print "REG_134 (AUX_REPLY_DATA) = ", (REG_134)

	# REG_138= apb_read_reg(0x138,int(Port), Device_RX )
	# print "REG_138 (AUX_REPLY_CODE) = ", (REG_138)

	# REG_13C= apb_read_reg(0x13C,int(Port), Device_RX )
	# print "REG_13C (AUX_REPLY_COUNT) = ", (REG_13C)

	# REG_140= apb_read_reg(0x140,int(Port), Device_RX )
	# print "REG_140 (INTERRUPT_STATUS) = ", (REG_140)

	# REG_144= apb_read_reg(0x144,int(Port), Device_RX )
	# print "REG_144 (INTERRUPT_MASK) = ", (REG_144)

	# REG_148= apb_read_reg(0x148,int(Port), Device_RX )
	# print "REG_148 (REPLY_DATA_COUNT) = ", (REG_148)

	# REG_14C= apb_read_reg(0x14C,int(Port), Device_RX )
	# print "REG_14C (AUX_STATUS) = ", (REG_14C)

	# REG_150= apb_read_reg(0x150,int(Port), Device_RX )
	# print "REG_150 (AUX_REPLY_CLOCK_WIDTH) = ", (REG_150)

	# REG_154= apb_read_reg(0x154,int(Port), Device_RX )
	# print "REG_154 (AUX_WAKE_ACK_DETECTED) = ", (REG_154)

	# REG_158= apb_read_reg(0x158,int(Port), Device_RX )
	# print "REG_158 (GP_HOST_TIMER) = ", (REG_158)

	print ""
	print "STREAM: ", Stream, " Register Read: "
	print ""

	REG_0180= apb_read_reg_984_DPTX(0x180+Offset,int(Port), Device_RX )
	print "REG_0180 (MAIN_STREAM_HTOTAL) = ", (REG_0180)

	REG_0184= apb_read_reg_984_DPTX(0x184+Offset,int(Port), Device_RX )
	print "REG_0184 (MAIN_STREAM_VTOTAL) = ", (REG_0184)

	REG_0188= apb_read_reg_984_DPTX(0x188+Offset,int(Port), Device_RX )
	print "REG_0188 (MAIN_STREAM_POLARITY) = ", (REG_0188)

	REG_018C= apb_read_reg_984_DPTX(0x18C+Offset,int(Port), Device_RX )
	print "REG_018C (MAIN_STREAM_HSWIDTH) = ", (REG_018C)

	REG_0190= apb_read_reg_984_DPTX(0x190+Offset,int(Port), Device_RX )
	print "REG_0190 (MAIN_STREAM_VSWIDTH) = ", (REG_0190)

	REG_0194= apb_read_reg_984_DPTX(0x194+Offset,int(Port), Device_RX )
	print "REG_0194 (MAIN_STREAM_HRES) = ", (REG_0194)

	REG_0198= apb_read_reg_984_DPTX(0x198+Offset,int(Port), Device_RX )
	print "REG_0198 (MAIN_STREAM_VRES) = ", (REG_0198)

	REG_019C= apb_read_reg_984_DPTX(0x19C+Offset,int(Port), Device_RX )
	print "REG_019C (MAIN_STREAM_HSTART) = ", (REG_019C)

	REG_01A0= apb_read_reg_984_DPTX(0x1A0+Offset,int(Port), Device_RX )
	print "REG_01A0 (MAIN_STREAM_VSTART) = ", (REG_01A0)

	REG_01A4= apb_read_reg_984_DPTX(0x1A4+Offset,int(Port), Device_RX )
	print "REG_01A4 (MAIN_STREAM_MISC0) = ", (REG_01A4)

	REG_01A8= apb_read_reg_984_DPTX(0x1A8+Offset,int(Port), Device_RX )
	print "REG_01A8 (MAIN_STREAM_MISC1) = ", (REG_01A8)

	REG_01AC= apb_read_reg_984_DPTX(0x1AC+Offset,int(Port), Device_RX )
	print "REG_01AC (MVID) = ", (REG_01AC)

	REG_01B0= apb_read_reg_984_DPTX(0x1B0+Offset,int(Port), Device_RX )
	print "REG_01B0 (TRANSFER_UNIT_CONFIG_SRC_0) = ", (REG_01B0)

	REG_01B4= apb_read_reg_984_DPTX(0x1B4+Offset,int(Port), Device_RX )
	print "REG_01B4 (NVID) = ", (REG_01B4)

	REG_01B8= apb_read_reg_984_DPTX(0x1B8+Offset,int(Port), Device_RX )
	print "REG_01B8 (USER_PIXEL_COUNT) = ", (REG_01B8)

	REG_01BC= apb_read_reg_984_DPTX(0x1BC+Offset,int(Port), Device_RX )
	print "REG_01BC (USER_DATA_COUNT) = ", (REG_01BC)

	REG_01C0= apb_read_reg_984_DPTX(0x1C0+Offset,int(Port), Device_RX )
	print "REG_01C0 (MAIN_STREAM_INTERLACED) = ", (REG_01C0)

	REG_01C4= apb_read_reg_984_DPTX(0x1C4+Offset,int(Port), Device_RX )
	print "REG_01C4 (USER_SYNC_POLARITY) = ", (REG_01C4)

	REG_01C8= apb_read_reg_984_DPTX(0x1C8+Offset,int(Port), Device_RX )
	print "REG_01C8 (USER_CONTROL) = ", (REG_01C8)

	REG_0500= apb_read_reg_984_DPTX(0x500,int(Port), Device_RX )
	print "REG_0500 (MST_ENABLE) = ", (REG_0500)

	REG_0504= apb_read_reg_984_DPTX(0x504,int(Port), Device_RX )
	print "REG_0504 (MST_PID_TABLE_INDEX) = ", (REG_0504)

	REG_0508= apb_read_reg_984_DPTX(0x504,int(Port), Device_RX )
	print "REG_0508 (MST_PID_TABLE_ENTRY) = ", (REG_0508)

	REG_050C= apb_read_reg_984_DPTX(0x50C,int(Port), Device_RX )
	print "REG_050C (SST_SOURCE_SELECT) = ", (REG_050C)

	REG_0510= apb_read_reg_984_DPTX(0x510,int(Port), Device_RX )
	print "REG_0510 (MST_ALLOCATION_TRIGGER) = ", (REG_0510)

	REG_0514= apb_read_reg_984_DPTX(0x514,int(Port), Device_RX )
	print "REG_0514 (MST_PID_TABLE_SELECT) = ", (REG_0514)

	REG_0518= apb_read_reg_984_DPTX(0x518,int(Port), Device_RX )
	print "REG_0518 (MST_ACTIVE_PAYLOAD_TABLE) = ", (REG_0518)

	REG_0520= apb_read_reg_984_DPTX(0x520,int(Port), Device_RX )
	print "REG_0520 (MST_ACTIVE) = ", (REG_0520)

	REG_0524= apb_read_reg_984_DPTX(0x524,int(Port), Device_RX )
	print "REG_0524 (MST_LINK_FRAME_COUNT) = ", (REG_0524)

	REG_0528= apb_read_reg_984_DPTX(0x528,int(Port), Device_RX )
	print "REG_0528 (MSO_CONFIGURATION) = ", (REG_0528)

	REG_0528= apb_read_reg_984_DPTX(0x528,int(Port), Device_RX )
	print "REG_0528 (MSO_CONFIGURATION) = ", (REG_0528)

def Ux983_APBs(var): 
	for var in range (0x00,138):
		print hex(var*4), hex(apb_read_reg(serAddr,var*4))
		
	for var in range (256,336):
		print hex(var*4), hex(apb_read_reg(serAddr,var*4))
		
	for var in range (448,457):
		print hex(var*4), hex(apb_read_reg(serAddr,var*4))

	for var in range (512,589+1):
		print hex(var*4), hex(apb_read_reg(serAddr,var*4))
		
	for var in range (640,760+1):
		print hex(var*4), hex(apb_read_reg(serAddr,var*4))

def HH983_APBs():
	print("Receiver core config")
	print("0x0 (reciver core enable) = " + hex(apb_read_reg(serAddr,0x0)))
	print("0x018 (misc_config) = " + hex(apb_read_reg(serAddr,0x018)))
	print("0x024 (request_error_count) = " + hex(apb_read_reg(serAddr,0x024)))
	print("0x028 (request_count) = " + hex(apb_read_reg(serAddr,0x028)))
	print("0x070 (max_lane_count) = " + hex(apb_read_reg(serAddr,0x070)))
	print("0x074 (max_link_rate) = " + hex(apb_read_reg(serAddr,0x074)))
	print("")
	print("PHY config and status")
	print("0x208 (phy_status) = " + hex(apb_read_reg(serAddr,0x208)))
	print("0x214 (min_voltage_swing) = " + hex(apb_read_reg(serAddr,0x214)))
	print("0x218 (min_pre_emphasis) = " + hex(apb_read_reg(serAddr,0x218)))
	print("0x208 (phy_status) = " + hex(apb_read_reg(serAddr,0x208)))
	print("")
	print("DPCD config space")
	print("0x400 (LANE01_status) = " + hex(apb_read_reg(serAddr,0x400)))
	print("0x404 (LANE23_status) = " + hex(apb_read_reg(serAddr,0x404)))
	print("---MSA Video Timings----")
	print("H Res: ", apb_read_reg(serAddr,0x500))
	print("H Pol: ", apb_read_reg(serAddr,0x504))
	hsync = apb_read_reg(serAddr,0x508)
	print("H Sync: ", apb_read_reg(serAddr,0x508))
	print("H Back Porch: ", apb_read_reg(serAddr,0x50C) - hsync)
	print("H Total: ", apb_read_reg(serAddr,0x510))

	print("V Res: ", apb_read_reg(serAddr,0x514))
	print("V Pol: ", apb_read_reg(serAddr,0x518))

	v_sync = apb_read_reg(serAddr,0x51c)
	print("V Sync Width: ", v_sync)
	print("V Back Porch: ", apb_read_reg(serAddr,0x520) - v_sync)
	print("V Total: ", apb_read_reg(serAddr,0x524))
	print("    ")
	print("MSA MISC0: ", apb_read_reg(serAddr,0x528))
	print("MSA_MISC1: ", apb_read_reg(serAddr,0x52C))
	print("MSA_MVID: ", hex(apb_read_reg(serAddr,0x530)))
	print("MSA_NVID: ", hex(apb_read_reg(serAddr,0x534)))
	print("MSA_VBID: ", hex(apb_read_reg(serAddr,0x538)))
	print("MSA Updated", apb_read_reg(serAddr,0x544))
	print("")
	print("HDCP Config")
	print("0x600 (HDCP_enable) = " + hex(apb_read_reg(serAddr,0x600)))
	print("0x604 (HDCP_mode_select) = " + hex(apb_read_reg(serAddr,0x604)))
	# print("0x608 (HDCP_KS_31_0) = " + hex(apb_read_reg(serAddr,0x608)))
	# print("0x60C (HDCP_KS_63_32) = " + hex(apb_read_reg(serAddr,0x60C)))
	# print("0x610 (HDCP_KM_31_0) = " + hex(apb_read_reg(serAddr,0x610)))
	# print("0x614 (HDCP_KM_55_32) = " + hex(apb_read_reg(serAddr,0x614)))
	print("0x618 (HDCP_AN_31_0) = " + hex(apb_read_reg(serAddr,0x618)))
	print("0x61C (HDCP_AN_63_32) = " + hex(apb_read_reg(serAddr,0x61C)))
	print("0x624 (HDCP_authentication_in_progress) = " + hex(apb_read_reg(serAddr,0x624)))
	print("0x628 (HDCP_status) = " + hex(apb_read_reg(serAddr,0x628)))
	print("0x62C (HDCP_CIPHER_CONTROL) = " + hex(apb_read_reg(serAddr,0x62C)))
	print("0x630 (HDCP_AKSV_31_0) = " + hex(apb_read_reg(serAddr,0x630)))
	print("0x634 (HDCP_AKSV_63_32) = " + hex(apb_read_reg(serAddr,0x634)))
	print("0x638 (HDCP_HW_BKSV_31_0) = " + hex(apb_read_reg(serAddr,0x638)))
	print("0x63C (HDCP_HW_BKSV_63_32) = " + hex(apb_read_reg(serAddr,0x63C)))
	print("0x650 (HDCP_REPEATER) = " + hex(apb_read_reg(serAddr,0x650)))
	print("0x654 (HDCP_stream_cipher_enable) = " + hex(apb_read_reg(serAddr,0x654)))
	print("0x658 (HDCP_MO_31_0) = " + hex(apb_read_reg(serAddr,0x658)))
	print("0x65C (HDCP_MO_63_32) = " + hex(apb_read_reg(serAddr,0x65C)))
	print("0x660 (HDCP_AES_INPUT_SELECT) = " + hex(apb_read_reg(serAddr,0x660)))
	print("0x664 (HDCP_AES_COUNTER_DISABLE) = " + hex(apb_read_reg(serAddr,0x664)))
	print("0x668 (HDCP_AES_COUNTER_ADVANCE) = " + hex(apb_read_reg(serAddr,0x668)))
	print("0x66C (HDCP_ENCRYPTION_CONTROL_FIELD_31_0) = " + hex(apb_read_reg(serAddr,0x66C)))
	print("0x670 (HDCP_ENCRYPTION_CONTROL_FIELD_63_32) = " + hex(apb_read_reg(serAddr,0x670)))
	print("0x678 (HDCP_RN_31_0) = " + hex(apb_read_reg(serAddr,0x678)))
	print("0x67C (HDCP_RN_63_32) = " + hex(apb_read_reg(serAddr,0x67C)))
	print("0x684 (HDCP_RNG_CIPHER_AN_31_0) = " + hex(apb_read_reg(serAddr,0x684)))
	print("0x688 (HDCP_RNG_CIPHER_AN_63_32) = " + hex(apb_read_reg(serAddr,0x688)))
	print("0x68C (HDCP_HOST_TIMER) = " + hex(apb_read_reg(serAddr,0x68C)))
	print("0x690 (HDCP_encryption_active) = " + hex(apb_read_reg(serAddr,0x690)))
	print("0x694 (HDCP_link_integrity_failure) = " + hex(apb_read_reg(serAddr,0x694)))
	print("0x698 (HDCP_content_type_select_31_0) = " + hex(apb_read_reg(serAddr,0x698)))
	print("0x69C (HDCP_content_type_select_63_32) = " + hex(apb_read_reg(serAddr,0x69C)))

def Ux948_Res_dump(desAlias0):
	time.sleep(1)
	board.WriteI2C(desAlias0,0x68,0x19) # H active High monitor
	Hhigh = board.ReadI2C(desAlias0, 0x69, 1)
	board.WriteI2C(desAlias0,0x68,0x09) # H active Low monitor
	Hlow = board.ReadI2C(desAlias0, 0x69, 1)
	board.WriteI2C(desAlias0,0x68,0x39) # V active High monitor
	Vhigh = board.ReadI2C(desAlias0, 0x69, 1)
	board.WriteI2C(desAlias0,0x68,0x29) # V active Low monitor
	Vlow = board.ReadI2C(desAlias0, 0x69, 1)
	mask = int('00111111',2)
	hlowmask = Hlow & mask
	hhighmask = Hhigh & mask
	vlowmask = Vlow & mask
	vhighmask = Vhigh & mask
	hhighmask = hhighmask << 6
	vhighmask = vhighmask << 6
	Hactive = hhighmask | hlowmask
	Vactive = vhighmask | vlowmask
	print Hactive ,"x", Vactive ,",", #print out detected Dimensions

def Ux98x_SERDES_Full_Diagnostics():
	time.sleep(0.1)
	if SER == "HH983" or SER == "Ux983" or SER == "Ux943A":
		board.WriteI2C(serAddr, 0x7, 0x88)  # Enable I2C Passthrough for FPD4 98x SER

	if SER == "Hx94x":
		board.WriteI2C(serAddr, 0x3, 0xDA)  # Enable I2C Passthrough for FPD4 98x SER



	if SER == "Ux94x":
		print"Ux94x Statuses"
		for x in range(20):
			print"Device_ID = ", hex(board.ReadI2C(serAddr, 0x0)), ",",
			print"GENERAL_STATUS = ", hex(board.ReadI2C(serAddr, 0xC))

			# Clear CRC Erorr"
			Reg_4 = board.ReadI2C(serAddr, 0x4)
			Reg_4_mask = Reg_4 | 0x20
			board.WriteI2C(serAddr, 0x4, Reg_4_mask)  # CRC Error Reset

		Reg_4 = board.ReadI2C(serAddr, 0x4)
		Reg_4_unmask = Reg_4 & 0xDF
		board.WriteI2C(serAddr, 0x4, Reg_4_unmask)  # CRC Error Reset Clear

		for x in range(20):
			print"CRC_0xA = ", hex(board.ReadI2C(serAddr, 0xA)), ",",
			print"CRC_0xB = ", hex(board.ReadI2C(serAddr, 0xB))


	if DES == "Ux948":
		print "Ux948 Statuses"
		for x in range(20):
			print"GENERAL_STATUS = ", hex(board.ReadI2C(desAlias0, 0x1C)), ",",
			print"DUAL_RX_CTL = ", hex(board.ReadI2C(desAlias0, 0x34)), ",",
			print"Mode_Sel = ", hex(board.ReadI2C(desAlias0, 0x37)), ",",
			Ux948_Res_dump(desAlias0)
			print"FPD_TX_MODE = ", hex(board.ReadI2C(desAlias0, 0x49))


	if SER == "HH983" or SER == "Ux983" or SER == "Ux943A" or SER == "Ux981":
		print"----------------------------------"
		print("Lock / Link Status")
		for x in range(10):
			print"Ser Reg 0xC = ", hex(board.ReadI2C(serAddr, 0xC, 1)), ",",
			print"Des Reg 0x53 = ", hex(board.ReadI2C(desAlias0, 0x53, 1)), ",",
			print"Des Reg 0x54 = ", hex(board.ReadI2C(desAlias0, 0x54, 1)), ",",
			board.WriteI2C(serAddr, 0x40, 18 * 4 + 1)
			board.WriteI2C(serAddr, 0x41, 0x4E)
			print"Des Reg 0x4E = ", hex(board.ReadI2C(desAlias0, 0x42))


	if VP and SER == "HH983" or SER == "Ux983" or SER == "Ux943A" or SER == "Ux981":
		print "----------------------------------"
		print ("VP Status")
		for x in range(10):
			board.WriteI2C(serAddr, 0x40, 0x33)
			board.WriteI2C(serAddr, 0x41, 0x30)
			print "VP_STATUS:", board.ReadI2C(serAddr, 0x42, 1), ",",

			board.WriteI2C(serAddr, 0x40, 0x33)
			board.WriteI2C(serAddr, 0x41, 0x31)
			print "VP_INTERRUPTS:", board.ReadI2C(serAddr, 0x42, 1)



	if SER == "Ux981":
		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0xe)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"INTR_STS_DPHY = 0x", hex(read_val)
		print"[1] IS_DPHY_LANE_SYNC_ERROR", (read_val & 0x2) >> 1
		print"[0] IS_DPHY_LANE_ERROR", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0xf)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_STATUS = 0x", hex(read_val)
		print"[4] C_LANE_ACTIVE", (read_val & 0x10) >> 4
		print"[3] D_LANE3_ACTIVE", (read_val & 0x8) >> 3
		print"[2] D_LANE2_ACTIVE", (read_val & 0x4) >> 2
		print"[1] D_LANE1_ACTIVE", (read_val & 0x2) >> 1
		print"[0] D_LANE0_ACTIVE", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x10)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_DLANE0 = 0x", hex(read_val)
		print"[4] EOT_SYNC_ERROR", (read_val & 0x10) >> 4
		print"[3] SOT_ERROR", (read_val & 0x8) >> 3
		print"[2] SOT_SYNC_ERROR", (read_val & 0x4) >> 2
		print"[1] CNTRL_ERR_HSRQST", (read_val & 0x2) >> 1
		print"[0] HS_RX_TO_ERROR", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x11)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_DLANE1 = 0x", hex(read_val)
		print"[4] EOT_SYNC_ERROR", (read_val & 0x10) >> 4
		print"[3] SOT_ERROR", (read_val & 0x8) >> 3
		print"[2] SOT_SYNC_ERROR", (read_val & 0x4) >> 2
		print"[1] CNTRL_ERR_HSRQST", (read_val & 0x2) >> 1
		print"[0] HS_RX_TO_ERROR", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x12)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_DLANE2 = 0x", hex(read_val)
		print"[4] EOT_SYNC_ERROR", (read_val & 0x10) >> 4
		print"[3] SOT_ERROR", (read_val & 0x8) >> 3
		print"[2] SOT_SYNC_ERROR", (read_val & 0x4) >> 2
		print"[1] CNTRL_ERR_HSRQST", (read_val & 0x2) >> 1
		print"[0] HS_RX_TO_ERROR", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x13)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_DLANE3 = 0x", hex(read_val)
		print"[4] EOT_SYNC_ERROR", (read_val & 0x10) >> 4
		print"[3] SOT_ERROR", (read_val & 0x8) >> 3
		print"[2] SOT_SYNC_ERROR", (read_val & 0x4) >> 2
		print"[1] CNTRL_ERR_HSRQST", (read_val & 0x2) >> 1
		print"[0] HS_RX_TO_ERROR", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x14)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_ERR_CLK_LANE = 0x", hex(read_val)
		print
		"[2] CNTRL_ERR_HSRQST_CLK", (read_val & 0x4) >> 2
		print"[0] HS RX TO ERROR_CLK", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x15)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_SYNC_STS = 0x", read_val
		print"[3] DLANE3_SYNC_STS", (read_val & 0x8) >> 3
		print"[2] DLANE2_SYNC_STS", (read_val & 0x4) >> 2
		print"[1] DLANE1_SYNC_STS", (read_val & 0x2) >> 1
		print"[0] DLANE0_SYNC_STS", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x23)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"INTR_STS_DSI_ERR = 0x", read_val
		print"[7] IS_INV_TYPE_GLW_ERR", (read_val & 0x80) >> 7
		print"[6] IS_INV_WC_GLW_ERR", (read_val & 0x40) >> 6
		print"[5] IS_INV_LEN_ERR", (read_val & 0x20) >> 5
		print"[4] IS_INV_VC_ERR", (read_val & 0x10) >> 4
		print"[3] IS_INV_DT_ERR", (read_val & 0x8) >> 3
		print"[2] IS_CHECKSUM_ERR", (read_val & 0x4) >> 2
		print"[1] IS_ECC_MULTI_ERR", (read_val & 0x2) >> 1
		print"[0] IS_ECC_SINGLE_ERR", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x2a)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_DSI_VC_DTYPE = 0x", read_val




	if SER == "HH983" and DPRX:
		print "----------------------------------"
		print ("DPRX Status")
		apb_write_reg(serAddr, 0x4F4, 0x00)  # Address [19:16]
		apb_write_reg(serAddr, 0x4F0, 0x03)
		apb_write_reg(serAddr, 0x4F4, 0x01)  # Address [15:8]
		apb_write_reg(serAddr, 0x4F0, 0x03)
		apb_write_reg(serAddr, 0x4F4, 0x00)  # Address [7:0]
		apb_write_reg(serAddr, 0x4F0, 0x03)
		apb_write_reg(serAddr, 0x4F0, 0x02)  # Read Strobe
		LINK_BW_SET = apb_read_reg(serAddr, 0x4F8)
		if LINK_BW_SET == 0:
			print "No Link Speed Detected"
		elif LINK_BW_SET == 0x06:
			print "Link Rate = 1.62Gbps/lane"
		elif LINK_BW_SET == 0x0A:
			print "Link Rate = 2.7Gbps/lane"
		elif LINK_BW_SET == 0x14:
			print "Link Rate = 5.4Gbps/lane"
		elif LINK_BW_SET == 0x1E:
			print "Link Rate = 8.1Gbps/lane"

		# Lane Count Check via Direct DPCD Access
		apb_write_reg(serAddr, 0x4F4, 0x00)  # Address [19:16]
		apb_write_reg(serAddr, 0x4F0, 0x03)
		apb_write_reg(serAddr, 0x4F4, 0x01)  # Address [15:8]
		apb_write_reg(serAddr, 0x4F0, 0x03)
		apb_write_reg(serAddr, 0x4F4, 0x01)  # Address [7:0]
		apb_write_reg(serAddr, 0x4F0, 0x03)
		apb_write_reg(serAddr, 0x4F0, 0x02)  # Read Strobe
		LANE_COUNT_SET = apb_read_reg(serAddr, 0x4F8)
		if LANE_COUNT_SET & 0x1F == 0:
			print "No Active DP Lanes Detected"
		elif LANE_COUNT_SET & 0x1F == 0x01:
			print "One DP Lane"
		elif LANE_COUNT_SET & 0x1F == 0x02:
			print "Two DP Lanes"
		elif LANE_COUNT_SET & 0x1F == 0x04:
			print "4 DP Lanes"

		print("H Res")
		print apb_read_reg(serAddr, 0x500)

		print("H POL")
		print apb_read_reg(serAddr, 0x504)

		print("H SYNC WIDTH")
		h_sync = apb_read_reg(serAddr, 0x508)
		print h_sync

		print("H BACK PORCH")
		H_Back = apb_read_reg(serAddr, 0x50C) - h_sync
		print H_Back

		print("H TOTAL")
		print apb_read_reg(serAddr, 0x510)

		print("V Res")
		print apb_read_reg(serAddr, 0x514)

		print("V POL")
		print apb_read_reg(serAddr, 0x518)

		print("V SYNC WIDTH")
		v_sync = apb_read_reg(serAddr, 0x51C)
		print v_sync

		print("V BACK PORCH ")
		v_back = apb_read_reg(serAddr, 0x520) - v_sync
		print v_back

		print("HV TOTAL")
		print apb_read_reg(serAddr, 0x524)

		print("MSA_MISC0")
		print apb_read_reg(serAddr, 0x528)

		print("MSA_MISC1")
		print apb_read_reg(serAddr, 0x52C)

		print("MSA_MVID")
		print apb_read_reg(serAddr, 0x530)

		print("MSA_NVID")
		print apb_read_reg(serAddr, 0x534)

		print("MSA_VBID")
		print apb_read_reg(serAddr, 0x538)

	if SER == "Ux983" or SER == "Ux943A":
		print "----------------------------------"
		print ("DPRX Status")
		print apb_read_reg(serAddr, 0x400) * 27, ("Rate")
		print apb_read_reg(serAddr, 0x404), ("Lanes")
		print hex(apb_read_reg(serAddr, 0x43c))
		print hex(apb_read_reg(serAddr, 0x440))
		print hex(apb_read_reg(serAddr, 0x18))
		print hex(apb_read_reg(serAddr, 0x48C))
		if apb_read_reg(serAddr, 0x48C) == 0:
			print "Video source is set to SST mode"
		if apb_read_reg(serAddr, 0x48C) == 1:
			print "Video source is set to MST mode"
		print "----------------------------------"

		if SER == "Ux983" or SER ==  "Ux943A" and SER_MSAs:
			if MST == 0:
				apb_write_reg(serAddr, 0x540, 0x0)
				print("H Res")
				print apb_read_reg(serAddr, 0x500)

				print("H POL")
				print apb_read_reg(serAddr, 0x504)

				print("H SYNC WIDTH")
				h_sync = apb_read_reg(serAddr, 0x508)
				print h_sync

				print("H BACK PORCH")
				H_Back = apb_read_reg(serAddr, 0x50C) - h_sync
				print H_Back

				print("H TOTAL")
				print apb_read_reg(serAddr, 0x510)

				print("V Res")
				print apb_read_reg(serAddr, 0x514)

				print("V POL")
				print apb_read_reg(serAddr, 0x518)

				print("V SYNC WIDTH")
				v_sync = apb_read_reg(serAddr, 0x51C)
				print v_sync

				print("V BACK PORCH ")
				v_back = apb_read_reg(serAddr, 0x520) - v_sync
				print v_back

				print("HV TOTAL")
				print apb_read_reg(serAddr, 0x524)

				print("MSA_MISC0")
				print apb_read_reg(serAddr, 0x528)

				print("MSA_MISC1")
				print apb_read_reg(serAddr, 0x52C)

				print("MSA_MVID")
				print apb_read_reg(serAddr, 0x530)

				print("MSA_NVID")
				print apb_read_reg(serAddr, 0x534)

				print("MSA_VBID")
				print apb_read_reg(serAddr, 0x538)

				print("SYMBOL ERRORs - Lane 0")
				print hex(apb_read_reg(serAddr, 0x490))

				print("SYMBOL ERRORs - Lane 1")
				print hex(apb_read_reg(serAddr, 0x494))

				print("SYMBOL ERRORs - Lane 2")
				print hex(apb_read_reg(serAddr, 0x498))

				print("SYMBOL ERRORs - Lane 3")
				print hex(apb_read_reg(serAddr, 0x49C))

			else:
				print "----------------------------------"
				print("## MST0")
				apb_write_reg(serAddr, 0x540, 0x0)
				print("H Res")
				print apb_read_reg(serAddr, 0x500)

				print("H POL")
				print apb_read_reg(serAddr, 0x504)

				print("H SYNC WIDTH")
				h_sync = apb_read_reg(serAddr, 0x508)
				print h_sync

				print("H BACK PORCH")
				H_Back = apb_read_reg(serAddr, 0x50C) - h_sync
				print H_Back

				print("H TOTAL")
				print apb_read_reg(serAddr, 0x510)

				print("V Res")
				print apb_read_reg(serAddr, 0x514)

				print("V POL")
				print apb_read_reg(serAddr, 0x518)

				print("V SYNC WIDTH")
				v_sync = apb_read_reg(serAddr, 0x51C)
				print v_sync

				print("V BACK PORCH ")
				v_back = apb_read_reg(serAddr, 0x520) - v_sync
				print v_back

				print("HV TOTAL")
				print apb_read_reg(serAddr, 0x524)

				print("MSA_MISC0")
				print apb_read_reg(serAddr, 0x528)

				print("MSA_MISC1")
				print apb_read_reg(serAddr, 0x52C)

				print("MSA_MVID")
				print apb_read_reg(serAddr, 0x530)

				print("MSA_NVID")
				print apb_read_reg(serAddr, 0x534)

				print("MSA_VBID")
				print apb_read_reg(serAddr, 0x538)

				print("SYMBOL ERRORs - Lane 0")
				print hex(apb_read_reg(serAddr, 0x490))

				print("SYMBOL ERRORs - Lane 1")
				print hex(apb_read_reg(serAddr, 0x494))

				print("SYMBOL ERRORs - Lane 2")
				print hex(apb_read_reg(serAddr, 0x498))

				print("SYMBOL ERRORs - Lane 3")
				print hex(apb_read_reg(serAddr, 0x49C))

				print("## MST1")
				apb_write_reg(serAddr, 0x540, 0x1)
				print("H Res")
				print apb_read_reg(serAddr, 0x500)

				print("H POL")
				print apb_read_reg(serAddr, 0x504)

				print("H SYNC WIDTH")
				h_sync = apb_read_reg(serAddr, 0x508)
				print h_sync

				print("H BACK PORCH")
				H_Back = apb_read_reg(serAddr, 0x50C) - h_sync
				print H_Back

				print("H TOTAL")
				print apb_read_reg(serAddr, 0x510)

				print("V Res")
				print apb_read_reg(serAddr, 0x514)

				print("V POL")
				print apb_read_reg(serAddr, 0x518)

				print("V SYNC WIDTH")
				v_sync = apb_read_reg(serAddr, 0x51C)
				print v_sync

				print("V BACK PORCH ")
				v_back = apb_read_reg(serAddr, 0x520) - v_sync
				print v_back

				print("HV TOTAL")
				print apb_read_reg(serAddr, 0x524)

				print("MSA_MISC0")
				print apb_read_reg(serAddr, 0x528)

				print("MSA_MISC1")
				print apb_read_reg(serAddr, 0x52C)

				print("MSA_MVID")
				print apb_read_reg(serAddr, 0x530)

				print("MSA_NVID")
				print apb_read_reg(serAddr, 0x534)

				print("MSA_VBID")
				print apb_read_reg(serAddr, 0x538)

				print("SYMBOL ERRORs - Lane 0")
				print hex(apb_read_reg(serAddr, 0x490))

				print("SYMBOL ERRORs - Lane 1")
				print hex(apb_read_reg(serAddr, 0x494))

				print("SYMBOL ERRORs - Lane 2")
				print hex(apb_read_reg(serAddr, 0x498))

				print("SYMBOL ERRORs - Lane 3")
				print hex(apb_read_reg(serAddr, 0x49C))

	if DES == "Ux984" or DES == "HH984":
		if DPTX:
			print "----------------------------------"
			print "DPTX Status"
			## AUX DP/eDP Train Status Read 0x202 and 0x203
			board.WriteI2C(desAlias0, 0x40, 0x2D)
			board.WriteI2C(desAlias0, 0x41, 0x93)
			print "Page11 reg 0x93 = ", hex(board.ReadI2C(desAlias0, 0x42, 1))
			for dpcdAddr in range(0x202, 0x204):
				apb_write_reg(desAlias0, 0x13C, 0x1)  # Clear AUX_Reply Count
				# Aux read transaction to read DPCD registers
				apb_write_reg(desAlias0, 0x108, dpcdAddr)  # aux address
				apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
				time.sleep(0.25)
				AUX_REPLY_COUNT = apb_read_reg(desAlias0, 0x13C)
				# print "AUX Reply Count:", AUX_REPLY_COUNT
				if AUX_REPLY_COUNT == 1:
					replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
					print "DPCD addr " + hex(dpcdAddr) + " is " + hex(replyData)
				else:
					print "No AUX Reply Detected"
					apb_write_reg(desAlias0, 0x108, 0x202)  # aux address
					apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
					time.sleep(0.25)
					replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
					apb_write_reg(desAlias0, 0x108, 0x202)  # aux address
					apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
					time.sleep(0.25)
					replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
					print "'DPCD addr " + hex(0x202) + " is " + hex(replyData)

					apb_write_reg(desAlias0, 0x108, 0x203)  # aux address
					apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
					time.sleep(0.25)
					replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
					apb_write_reg(desAlias0, 0x108, 0x203)  # aux address
					apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
					time.sleep(0.25)
					replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
					print "'DPCD addr " + hex(0x203) + " is " + hex(replyData)

			for dpcdAddr in range(0x100, 0x101):
				# Aux read transaction to read DPCD registers
				apb_write_reg(desAlias0, 0x108, dpcdAddr)  # aux address
				apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
				time.sleep(0.25)
				replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
				print "DPCD addr " + hex(dpcdAddr) + " is " + hex(replyData)
				if replyData == 10:
					print "DPTX = 2.7 Gbps"
				if replyData == 6:
					print "DPTX = 1.62 Gbps"
				if replyData == 20:
					print "DPTX = 5.4 Gbps"
				if replyData == 30:
					print "DPTX = 8.1 Gbps"

			for dpcdAddr in range(0x101, 0x102):
				# Aux read transaction to read DPCD registers
				apb_write_reg(desAlias0, 0x108, dpcdAddr)  # aux address
				apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
				time.sleep(0.25)
				replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
				print "DPCD addr " + hex(dpcdAddr) + " is " + hex(replyData)
				if replyData == 0x84:
					print "DP_Lanes = 4"
		print "----------------------------------"
		print "Des FIFO = ", hex(apb_read_reg(desAlias0, 0x1CC))

		if DTGs:
			print "----------------------------------"
			print "DTG Port 0 Timing:"
			measure = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]

			board.WriteI2C(desAlias0, 0x40, 0x53)
			board.WriteI2C(desAlias0, 0x41, 0x40)
			for x in range(0, 16, 1):
				measure[x] = board.ReadI2C(desAlias0, 0x42, 1)

			Htotal = (measure[0] << 8) | measure[1]
			print "Htotal = ", Htotal
			Vtotal = (measure[2] << 8) | measure[3]
			print "Vtotal = ", Vtotal
			Hactive = (measure[4] << 8) | measure[5]
			print "Hactive = ", Hactive
			Vactive = (measure[6] << 8) | measure[7]
			print "Vactive = ", Vactive
			Hstart = (measure[8] << 8) | measure[9]
			print "Hstart = ", Hstart
			Vstart = (measure[10] << 8) | measure[11]
			Hsync = (measure[12] << 8) | measure[13]
			print "Hsync = ", Hsync
			Vsync = (measure[14] << 8) | measure[15]
			print "Vsync = ", Vsync

			Vback = Vstart - Vsync
			print "Vback = ", Vback

			Vfront = Vtotal - Vactive - Vsync - Vback
			print "Vfront = ", Vfront

		if DP0 and DES == "Ux984":
			print "----------------------------------"
			print "Print Des MSAs"
			Measure_Video_DPTX(desAlias0, 0, 1)
			print "----------------------------------"
			print "Ux984 DPTX APBs"
			Ux984_APB_Dump(0,desAlias0)
		if DP0 and DES == "HH984":
			print "----------------------------------"
			print "Print Des MSAs"
			Measure_Video_DPTX_HH(desAlias0, 0, 1)

		if DP1 and DES == "Ux984":
			print "----------------------------------"
			print "Print Des MSAs"
			Measure_Video_DPTX(desAlias0, 1, 1)
		if DP1 and DES == "HH984":
			print "----------------------------------"
			print "Print Des MSAs"
			Measure_Video_DPTX_HH(desAlias0, 1, 1)
	if DES == "Ux988" :
		print "----------------------------------"
		print "Ux988 Status"
		print "DES_Addr = ", hex(board.ReadI2C(desAlias0, 0x0))
		for x in range(10):
			# print ("Link and Lock Status")
			print "Ser Reg 0xC = ", hex(board.ReadI2C(serAddr, 0xC, 1)), ",",
			print "Des Reg 0x53 = ", hex(board.ReadI2C(desAlias0, 0x53, 1)), ",",
			print "Des Reg 0x54 = ", hex(board.ReadI2C(desAlias0, 0x54, 1)), ",",
			board.WriteI2C(serAddr, 0x40, 18 * 4 + 1)
			board.WriteI2C(serAddr, 0x41, 0x4E)
			print "Des Reg 0x4E = ", hex(board.ReadI2C(desAlias0, 0x42))


		measure = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]

		board.WriteI2C(desAlias0, 0x40, 0x53)
		board.WriteI2C(desAlias0, 0x41, 0x40)
		for x in range(0, 16, 1):
			measure[x] = board.ReadI2C(desAlias0, 0x42, 1)
		print "----------------------------------"
		print "Ux988 DTGs"
		Htotal = (measure[0] << 8) | measure[1]
		print "Htotal = ", Htotal
		Vtotal = (measure[2] << 8) | measure[3]
		print "Vtotal = ", Vtotal
		Hactive = (measure[4] << 8) | measure[5]
		print "Hactive = ", Hactive
		Vactive = (measure[6] << 8) | measure[7]
		print "Vactive = ", Vactive
		Hstart = (measure[8] << 8) | measure[9]
		print "Hstart = ", Hstart
		Vstart = (measure[10] << 8) | measure[11]
		Hsync = (measure[12] << 8) | measure[13]
		print "Hsync = ", Hsync
		Vsync = (measure[14] << 8) | measure[15]
		print "Vsync = ", Vsync

		Vback = Vstart - Vsync
		print "Vback = ", Vback

		Vfront = Vtotal - Vactive - Vsync - Vback
		print "Vfront = ", Vfront
		board.WriteI2C(desAlias0, 0x41, 0x70)

		board.WriteI2C(desAlias0, 0x41, 0xA0)

		print "FPD IV Link Layer Timing:"

		board.WriteI2C(desAlias0, 0x40, 0x4B)
		board.WriteI2C(desAlias0, 0x41, 0x39)

		for x in range(0, 12, 1):
			measure[x] = board.ReadI2C(desAlias0, 0x42)

		Stream0 = (measure[1] << 8) | measure[0]
		Stream1 = (measure[3] << 8) | measure[2]
		Stream2 = (measure[5] << 8) | measure[4]
		Stream3 = (measure[7] << 8) | measure[6]
		Stream4 = (measure[9] << 8) | measure[8]
		Stream5 = (measure[11] << 8) | measure[10]

		print "Stream 0 Hactive = ", Stream0
		print "Stream 1 Hactive = ", Stream1
		print "Stream 2 Hactive = ", Stream2
		print "Stream 3 Hactive = ", Stream3
		print "Stream 4 Hactive = ", Stream4
		print "Stream 5 Hactive = ", Stream5

	if SER == "Ux983":
		print "-------------------------"
		print "Ux983_APB_dump"
		Ux983_APBs(0)

	if SER == "HH983":
		print "-------------------------"
		print "HH983_APB_dump"
		HH983_APBs()








Ux98x_SERDES_Full_Diagnostics()
time.sleep(0.1)

## TI Confidential - NDA Restrictions
##
## Copyright 2018 Texas Instruments Incorporated. All rights reserved.
##
## IMPORTANT: Your use of this Software is limited to those specific rights
## granted under the terms of a software license agreement between the user who
## downloaded the software, his/her employer (which must be your employer) and
## Texas Instruments Incorporated (the License). You may not use this Software
## unless you agree to abide by the terms of the License. The License limits your
## use, and you acknowledge, that the Software may not be modified, copied or
## distributed unless embedded on a Texas Instruments microcontroller which is
## integrated into your product. Other than for the foregoing purpose, you may
## not use, reproduce, copy, prepare derivative works of, modify, distribute,
## perform, display or sell this Software and/or its documentation for any
## purpose.
##
## YOU FURTHER ACKNOWLEDGE AND AGREE THAT THE SOFTWARE AND DOCUMENTATION ARE
## PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
## INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY, TITLE,
## NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TEXAS
## INSTRUMENTS OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER CONTRACT,
## NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR OTHER LEGAL
## EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES INCLUDING BUT NOT
## LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL
## DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS,
## TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT
## LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
##
## Should you have any questions regarding your right to use this Software,
## contact Texas Instruments Incorporated at www.TI.com.
## Debug Script Version 1
import time

#######################User_Input############################
serAddr = 0x18
desAlias0 = 0x58
SER = "Ux983"  # Chosse HH983 or Ux983 or Ux943A or Ux981 or Ux94x
DES = "Ux984"  # Chosse HH984 or Ux984 or Ux988 or Ux948
MST = 0        # For Ux983 Select 0 for SST and 1 for MST mode
DP0 = 1        # For Ux984 Enable DPTX port0 diagnostics
DP1 = 0        # For Ux984 Enable DPTX port1 diagnostics

##################Keep Always ON#############################
VP = 1  # Enable VP diagnostics
SER_MSAs = 1  # Dump 983 SER MSAs
DTGs = 1  # dump DES DTGs
DPRX = 1  # Enable 983 DPRX diagnostics
DPTX = 1  # Enable 984 DPTX diagnostics
#############################################################

def apb_read_reg(DevAddrRxMain, addr16b):
    APB_CTL = 0x48
    APB_AUTO_INC = {'pos': 2, 'wid': 1}
    APB_READ = {'pos': 1, 'wid': 1}
    APB_ENABLE = {'pos': 0, 'wid': 1}
    APB_ADR0 = 0x49
    APB_ADR1 = 0x4A
    APB_DATA0 = 0x4B
    APB_DATA1 = 0x4C
    APB_DATA2 = 0x4D
    APB_DATA3 = 0x4E
    addr16b_lsb = addr16b & 0xFF
    addr16b_msb = (addr16b & 0xFF00) >> 8
    board.WriteI2C(DevAddrRxMain, APB_ADR0, addr16b_lsb)
    board.WriteI2C(DevAddrRxMain, APB_ADR1, addr16b_msb)
    board.WriteI2C(DevAddrRxMain, APB_CTL, 0x03)
    apbData0 = board.ReadI2C(DevAddrRxMain, APB_DATA0)
    apbData1 = board.ReadI2C(DevAddrRxMain, APB_DATA1)
    apbData2 = board.ReadI2C(DevAddrRxMain, APB_DATA2)
    apbData3 = board.ReadI2C(DevAddrRxMain, APB_DATA3)
    apbData = (apbData3 << 24) | (apbData2 << 16) | (apbData1 << 8) | (apbData0 << 0)
    val32bit = apbData
    return val32bit


def apb_write_reg(DevAddrRxMain, addr16b, data32b):
    APB_CTL = 0x48
    APB_AUTO_INC = {'pos': 2, 'wid': 1}
    APB_READ = {'pos': 1, 'wid': 1}
    APB_ENABLE = {'pos': 0, 'wid': 1}
    APB_ADR0 = 0x49
    APB_ADR1 = 0x4A
    APB_DATA0 = 0x4B
    APB_DATA1 = 0x4C
    APB_DATA2 = 0x4D
    APB_DATA3 = 0x4E
    addr16b_lsb = addr16b & 0xFF
    addr16b_msb = (addr16b & 0xFF00) >> 8
    board.WriteI2C(DevAddrRxMain, APB_ADR0, addr16b_lsb)
    board.WriteI2C(DevAddrRxMain, APB_ADR1, addr16b_msb)
    # print 'data32b', data32b
    apbData0 = int((data32b & 0x000000FF) >> 0)
    # print 'type', type(apbData0), apbData0
    apbData1 = int((data32b & 0x0000FF00) >> 8)
    apbData2 = int((data32b & 0x00FF0000) >> 16)
    apbData3 = int((data32b & 0xFF000000) >> 24)
    board.WriteI2C(DevAddrRxMain, APB_DATA0, apbData0)
    board.WriteI2C(DevAddrRxMain, APB_DATA1, apbData1)
    board.WriteI2C(DevAddrRxMain, APB_DATA2, apbData2)
    board.WriteI2C(DevAddrRxMain, APB_DATA3, apbData3)
    board.WriteI2C(DevAddrRxMain, APB_CTL, 0x01)


def MSA_apb_read_reg(addr16b, channel, Device_ID):
    APB_CTL = 0x48
    APB_AUTO_INC = {'pos': 2, 'wid': 1}
    APB_READ = {'pos': 1, 'wid': 1}
    APB_ENABLE = {'pos': 0, 'wid': 1}
    APB_ADR0 = 0x49
    APB_ADR1 = 0x4A
    APB_DATA0 = 0x4B
    APB_DATA1 = 0x4C
    APB_DATA2 = 0x4D
    APB_DATA3 = 0x4E

    if channel == 0:
        page = 0x03
    elif channel == 1:
        page = 0x0B
    else:
        page = 0x03

    addr16b_lsb = addr16b & 0xFF
    addr16b_msb = (addr16b & 0xFF00) >> 8

    board.WriteI2C(Device_ID, APB_ADR0, addr16b_lsb)

    board.WriteI2C(Device_ID, APB_ADR1, addr16b_msb)

    board.WriteI2C(Device_ID, APB_CTL, page)

    apbData0 = board.ReadI2C(Device_ID, APB_DATA0)

    apbData1 = board.ReadI2C(Device_ID, APB_DATA1)

    apbData2 = board.ReadI2C(Device_ID, APB_DATA2)

    apbData3 = board.ReadI2C(Device_ID, APB_DATA3)

    apbData = (apbData3 << 24) + (apbData2 << 16) + (apbData1 << 8) + (apbData0 << 0)
    val32bit = apbData

    return val32bit


def Measure_Video_DPTX(desAlias0, Port, PRNT_STATUS):
    print("")
    Offset = 0x00

    htotal = MSA_apb_read_reg(0x180 + Offset, int(Port), desAlias0)

    vtotal = MSA_apb_read_reg(0x184 + Offset, int(Port), desAlias0)

    hres = MSA_apb_read_reg(0x194 + Offset, int(Port), desAlias0)

    vres = MSA_apb_read_reg(0x198 + Offset, int(Port), desAlias0)

    hstart = MSA_apb_read_reg(0x19C + Offset, int(Port), desAlias0)

    vstart = MSA_apb_read_reg(0x1A0 + Offset, int(Port), desAlias0)

    hswidth = MSA_apb_read_reg(0x18C + Offset, int(Port), desAlias0)

    vswidth = MSA_apb_read_reg(0x190 + Offset, int(Port), desAlias0)

    if PRNT_STATUS == 1:
        print("Port", Port, ": DPTX VIDEO RESOLUTION:")
        print("Port", Port, ": htotal (0x180) = " + str(htotal))
        print("Port", Port, ": vtotal (0x184) = " + str(vtotal))
        print("Port", Port, ": hres (0x18C) = " + str(hres))
        print("Port", Port, ": vres (0x190) = " + str(vres))
        print("Port", Port, ": hstart (0x19C) = " + str(hstart))
        print("Port", Port, ": vstart (0x1A0) = " + str(vstart))
        print("Port", Port, ": hswidth (0x18C) = " + str(hswidth))
        print("Port", Port, ": vswidth (0x18C) = " + str(vswidth))

    return htotal, hres, vtotal, vres

def Measure_Video_DPTX_HH(desAlias0, Port, PRNT_STATUS):
        print("")
        Offset = 0x00

        htotal = MSA_apb_read_reg(0x820 + Offset, int(Port), desAlias0)

        vtotal = MSA_apb_read_reg(0x824 + Offset, int(Port), desAlias0)

        hres = MSA_apb_read_reg(0x834 + Offset, int(Port), desAlias0)

        vres = MSA_apb_read_reg(0x838 + Offset, int(Port), desAlias0)

        hstart = MSA_apb_read_reg(0x83C + Offset, int(Port), desAlias0)

        vstart = MSA_apb_read_reg(0x840 + Offset, int(Port), desAlias0)

        hswidth = MSA_apb_read_reg(0x82C + Offset, int(Port), desAlias0)

        vswidth = MSA_apb_read_reg(0x830 + Offset, int(Port), desAlias0)

        if PRNT_STATUS == 1:
            print("Port", Port, ": DPTX VIDEO RESOLUTION:")
            print("Port", Port, ": htotal (0x820) = " + str(htotal))
            print("Port", Port, ": vtotal (0x824) = " + str(vtotal))
            print("Port", Port, ": hres (0x834) = " + str(hres))
            print("Port", Port, ": vres (0x838) = " + str(vres))
            print("Port", Port, ": hstart (0x83C) = " + str(hstart))
            print("Port", Port, ": vstart (0x840) = " + str(vstart))
            print("Port", Port, ": hswidth (0x82C) = " + str(hswidth))
            print("Port", Port, ": vswidth (0x830) = " + str(vswidth))

        return htotal, hres, vtotal, vres

def apb_read_reg_984_DPTX(addr16b, channel, Device_ID):
	APB_CTL = 0x48
	APB_AUTO_INC = {'pos': 2, 'wid': 1}
	APB_READ = {'pos': 1, 'wid': 1}
	APB_ENABLE = {'pos': 0, 'wid': 1}
	APB_ADR0 = 0x49
	APB_ADR1 = 0x4A
	APB_DATA0 = 0x4B
	APB_DATA1 = 0x4C
	APB_DATA2 = 0x4D
	APB_DATA3 = 0x4E

	if channel == 0:
		page = 0x03
	elif channel == 1:
		page = 0x0B
	else:
		page = 0x03

	addr16b_lsb = addr16b & 0xFF
	addr16b_msb = (addr16b & 0xFF00) >> 8
	##print 'READ inst'
	board.WriteI2C(Device_ID, APB_ADR0, addr16b_lsb)
	board.WriteI2C(Device_ID, APB_ADR1, addr16b_msb)
	board.WriteI2C(Device_ID, APB_CTL, page)
	apbData0 = board.ReadI2C(Device_ID, APB_DATA0)
	apbData1 = board.ReadI2C(Device_ID, APB_DATA1)
	apbData2 = board.ReadI2C(Device_ID, APB_DATA2)
	apbData3 = board.ReadI2C(Device_ID, APB_DATA3)
	apbData = (apbData3 << 24) + (apbData2 << 16) + (apbData1 << 8) + (apbData0 << 0)
	val32bit = apbData
	Device_ID = 0x00
	return val32bit

def Ux984_APB_Dump(Port,Device_RX):
	Stream = 0 # 0, 1, 2, or 3
	if Stream == 0 :
		Offset = 0x00
	elif Stream == 1:
		Offset = 0x400
	elif Stream == 2:
		Offset = 0x420
	elif Stream == 3:
		Offset = 0x500
	else:
		Offset = 0x00
	print "PORT ",Port," DPTX APB Dump: Main Stream Attributes"

	REG_000= apb_read_reg_984_DPTX(0x000,int(Port), Device_RX )
	print "REG_000 (LINK_BW_SET) = ", (REG_000)

	REG_004= apb_read_reg_984_DPTX(0x004,int(Port), Device_RX )
	print "REG_004 (LANE_COUNT_SET) = ", (REG_004)

	REG_008= apb_read_reg_984_DPTX(0x008,int(Port), Device_RX )
	print "REG_008 (ENHANCED_FRAME_EN) = ", (REG_008)

	REG_00C= apb_read_reg_984_DPTX(0x00C,int(Port), Device_RX )
	print "REG_00C (TRAINING_PATTERN_SET) = ", (REG_00C)

	REG_010= apb_read_reg_984_DPTX(0x010,int(Port), Device_RX )
	print "REG_010 (LINK_QUAL_PATTERN_SET) = ", (REG_010)

	REG_014= apb_read_reg_984_DPTX(0x014,int(Port), Device_RX )
	print "REG_014 (SCRAMBLING_DISABLE) = ", (REG_014)

	REG_018= apb_read_reg_984_DPTX(0x018,int(Port), Device_RX )
	print "REG_018 (DOWNSPREAD_CTRL) = ", (REG_018)

	REG_01C= apb_read_reg_984_DPTX(0x01C,int(Port), Device_RX )
	print "REG_01C (EDP_CAPABILITY_CONFIG) = ", (REG_01C)

	REG_020= apb_read_reg_984_DPTX(0x020,int(Port), Device_RX )
	print "REG_020 (HBR2_COMPLIANCE_SCRAMBLER_RESET) = ", (REG_020)

	REG_024= apb_read_reg_984_DPTX(0x024,int(Port), Device_RX )
	print "REG_024 (DISPLAYPORT_VERSION) = ", (REG_024)

	REG_028= apb_read_reg_984_DPTX(0x028,int(Port), Device_RX )
	print "REG_024 (PHY_POWER_STATE) = ", (REG_028)

	REG_02C= apb_read_reg_984_DPTX(0x02C,int(Port), Device_RX )
	print "REG_02C (LANE_REMAP_CONTROL) = ", (REG_02C)

	REG_030= apb_read_reg_984_DPTX(0x030,int(Port), Device_RX )
	print "REG_030 (CUSTOM_80BIT_PATTERN_0) = ", (REG_030)

	REG_034= apb_read_reg_984_DPTX(0x034,int(Port), Device_RX )
	print "REG_034 (CUSTOM_80BIT_PATTERN_1) = ", (REG_034)

	REG_038= apb_read_reg_984_DPTX(0x038,int(Port), Device_RX )
	print "REG_038 (CUSTOM_80BIT_PATTERN_2) = ", (REG_038)

	REG_060= apb_read_reg_984_DPTX(0x060,int(Port), Device_RX )
	print "REG_060 (FEC_ENABLE) = ", (REG_060)

	REG_080= apb_read_reg_984_DPTX(0x080,int(Port), Device_RX )
	print "REG_080 (TRANSMITTER_OUTPUT_ENABLE) = ", (REG_080)

	REG_084= apb_read_reg_984_DPTX(0x084,int(Port), Device_RX )
	print "REG_084 (VIDEO_STREAM_ENABLE) = ", (REG_084)

	REG_088= apb_read_reg_984_DPTX(0x088,int(Port), Device_RX )
	print "REG_088 (SECONDARY_STREAM_ENABLE) = ", (REG_088)

	REG_08C= apb_read_reg_984_DPTX(0x08C,int(Port), Device_RX )
	print "REG_088 (SECONDARY_DATA_WINDOW) = ", (REG_08C)

	REG_090= apb_read_reg_984_DPTX(0x090,int(Port), Device_RX )
	print "REG_090 (SOFT_RESET) = ", (REG_090)

	REG_094= apb_read_reg_984_DPTX(0x094,int(Port), Device_RX )
	print "REG_094 (INPUT_SOURCE_ENABLE) = ", (REG_094)

	REG_098= apb_read_reg_984_DPTX(0x098,int(Port), Device_RX )
	print "REG_098 (FEC_ENABLE) = ", (REG_098)

	REG_0C0= apb_read_reg_984_DPTX(0x0C0,int(Port), Device_RX )
	print "REG_0C0 (ORCE_SCRAMBLER_RESET) = ", (REG_0C0)

	REG_0C4= apb_read_reg_984_DPTX(0x0C4,int(Port), Device_RX )
	print "REG_0C4 (USER_CONTROL_STATUS) = ", (REG_0C4)

	REG_0C8= apb_read_reg_984_DPTX(0x0C8,int(Port), Device_RX )
	print "REG_0C8 (USER_DATA_CONTROL) = ", (REG_0C8)

	REG_0F8= apb_read_reg_984_DPTX(0x0F8,int(Port), Device_RX )
	print "REG_0F8 (CORE_CAPABILITIES) = ", (REG_0F8)

	REG_0FC= apb_read_reg_984_DPTX(0x0FC,int(Port), Device_RX )
	print "REG_0FC (CORE_ID) = ", (REG_0FC)

	REG_100= apb_read_reg_984_DPTX(0x100,int(Port), Device_RX )
	print "REG_100 (AUX_COMMAND) = ", (REG_100)

	REG_104= apb_read_reg_984_DPTX(0x104,int(Port), Device_RX )
	print "REG_104 (AUX_WRITE_FIFO) = ", (REG_104)

	REG_108= apb_read_reg_984_DPTX(0x108,int(Port), Device_RX )
	print "REG_108 (AUX_ADDRESS) = ", (REG_108)

	REG_10C= apb_read_reg_984_DPTX(0x10C,int(Port), Device_RX )
	print "REG_10C (AUX_CLOCK_DIVIDER) = ", (REG_10C)

	REG_110= apb_read_reg_984_DPTX(0x110,int(Port), Device_RX )
	print "REG_110 (AUX_REPLY_TIMEOUT_INTERVAL) = ", (REG_110)

	REG_128= apb_read_reg_984_DPTX(0x128,int(Port), Device_RX )
	print "REG_128 (SINK_HPD_STATE) = ", (REG_128)

	REG_130= apb_read_reg_984_DPTX(0x130,int(Port), Device_RX )
	print "REG_130 (INTERRUPT_STATE) = ", (REG_130)

	REG_134= apb_read_reg_984_DPTX(0x134,int(Port), Device_RX )
	print "REG_134 (AUX_REPLY_DATA) = ", (REG_134)

	REG_138= apb_read_reg_984_DPTX(0x138,int(Port), Device_RX )
	print "REG_138 (AUX_REPLY_CODE) = ", (REG_138)

	REG_13C= apb_read_reg_984_DPTX(0x13C,int(Port), Device_RX )
	print "REG_13C (AUX_REPLY_COUNT) = ", (REG_13C)

	REG_140= apb_read_reg_984_DPTX(0x140,int(Port), Device_RX )
	print "REG_140 (INTERRUPT_STATUS) = ", (REG_140)

	REG_144= apb_read_reg_984_DPTX(0x144,int(Port), Device_RX )
	print "REG_144 (INTERRUPT_MASK) = ", (REG_144)

	REG_148= apb_read_reg_984_DPTX(0x148,int(Port), Device_RX )
	print "REG_148 (REPLY_DATA_COUNT) = ", (REG_148)

	REG_14C= apb_read_reg_984_DPTX(0x14C,int(Port), Device_RX )
	print "REG_14C (AUX_STATUS) = ", (REG_14C)

	REG_150= apb_read_reg_984_DPTX(0x150,int(Port), Device_RX )
	print "REG_150 (AUX_REPLY_CLOCK_WIDTH) = ", (REG_150)

	REG_154= apb_read_reg_984_DPTX(0x154,int(Port), Device_RX )
	print "REG_154 (AUX_WAKE_ACK_DETECTED) = ", (REG_154)

	REG_158= apb_read_reg_984_DPTX(0x158,int(Port), Device_RX )
	print "REG_158 (GP_HOST_TIMER) = ", (REG_158)

	print ""
	print "STREAM: ", Stream, " Register Read: "
	print ""

	REG_0180= apb_read_reg_984_DPTX(0x180+Offset,int(Port), Device_RX )
	print "REG_0180 (MAIN_STREAM_HTOTAL) = ", (REG_0180)

	REG_0184= apb_read_reg_984_DPTX(0x184+Offset,int(Port), Device_RX )
	print "REG_0184 (MAIN_STREAM_VTOTAL) = ", (REG_0184)

	REG_0188= apb_read_reg_984_DPTX(0x188+Offset,int(Port), Device_RX )
	print "REG_0188 (MAIN_STREAM_POLARITY) = ", (REG_0188)

	REG_018C= apb_read_reg_984_DPTX(0x18C+Offset,int(Port), Device_RX )
	print "REG_018C (MAIN_STREAM_HSWIDTH) = ", (REG_018C)

	REG_0190= apb_read_reg_984_DPTX(0x190+Offset,int(Port), Device_RX )
	print "REG_0190 (MAIN_STREAM_VSWIDTH) = ", (REG_0190)

	REG_0194= apb_read_reg_984_DPTX(0x194+Offset,int(Port), Device_RX )
	print "REG_0194 (MAIN_STREAM_HRES) = ", (REG_0194)

	REG_0198= apb_read_reg_984_DPTX(0x198+Offset,int(Port), Device_RX )
	print "REG_0198 (MAIN_STREAM_VRES) = ", (REG_0198)

	REG_019C= apb_read_reg_984_DPTX(0x19C+Offset,int(Port), Device_RX )
	print "REG_019C (MAIN_STREAM_HSTART) = ", (REG_019C)

	REG_01A0= apb_read_reg_984_DPTX(0x1A0+Offset,int(Port), Device_RX )
	print "REG_01A0 (MAIN_STREAM_VSTART) = ", (REG_01A0)

	REG_01A4= apb_read_reg_984_DPTX(0x1A4+Offset,int(Port), Device_RX )
	print "REG_01A4 (MAIN_STREAM_MISC0) = ", (REG_01A4)

	REG_01A8= apb_read_reg_984_DPTX(0x1A8+Offset,int(Port), Device_RX )
	print "REG_01A8 (MAIN_STREAM_MISC1) = ", (REG_01A8)

	REG_01AC= apb_read_reg_984_DPTX(0x1AC+Offset,int(Port), Device_RX )
	print "REG_01AC (MVID) = ", (REG_01AC)

	REG_01B0= apb_read_reg_984_DPTX(0x1B0+Offset,int(Port), Device_RX )
	print "REG_01B0 (TRANSFER_UNIT_CONFIG_SRC_0) = ", (REG_01B0)

	REG_01B4= apb_read_reg_984_DPTX(0x1B4+Offset,int(Port), Device_RX )
	print "REG_01B4 (NVID) = ", (REG_01B4)

	REG_01B8= apb_read_reg_984_DPTX(0x1B8+Offset,int(Port), Device_RX )
	print "REG_01B8 (USER_PIXEL_COUNT) = ", (REG_01B8)

	REG_01BC= apb_read_reg_984_DPTX(0x1BC+Offset,int(Port), Device_RX )
	print "REG_01BC (USER_DATA_COUNT) = ", (REG_01BC)

	REG_01C0= apb_read_reg_984_DPTX(0x1C0+Offset,int(Port), Device_RX )
	print "REG_01C0 (MAIN_STREAM_INTERLACED) = ", (REG_01C0)

	REG_01C4= apb_read_reg_984_DPTX(0x1C4+Offset,int(Port), Device_RX )
	print "REG_01C4 (USER_SYNC_POLARITY) = ", (REG_01C4)

	REG_01C8= apb_read_reg_984_DPTX(0x1C8+Offset,int(Port), Device_RX )
	print "REG_01C8 (USER_CONTROL) = ", (REG_01C8)

	REG_01CC= apb_read_reg_984_DPTX(0x1CC+Offset,int(Port), Device_RX )
	print "REG_01CC (USER_CONTROL) = ", (REG_01CC)

	REG_0500= apb_read_reg_984_DPTX(0x500,int(Port), Device_RX )
	print "REG_0500 (MST_ENABLE) = ", (REG_0500)

	REG_0504= apb_read_reg_984_DPTX(0x504,int(Port), Device_RX )
	print "REG_0504 (MST_PID_TABLE_INDEX) = ", (REG_0504)

	REG_0508= apb_read_reg_984_DPTX(0x504,int(Port), Device_RX )
	print "REG_0508 (MST_PID_TABLE_ENTRY) = ", (REG_0508)

	REG_050C= apb_read_reg_984_DPTX(0x50C,int(Port), Device_RX )
	print "REG_050C (SST_SOURCE_SELECT) = ", (REG_050C)

	REG_0510= apb_read_reg_984_DPTX(0x510,int(Port), Device_RX )
	print "REG_0510 (MST_ALLOCATION_TRIGGER) = ", (REG_0510)

	REG_0514= apb_read_reg_984_DPTX(0x514,int(Port), Device_RX )
	print "REG_0514 (MST_PID_TABLE_SELECT) = ", (REG_0514)

	REG_0518= apb_read_reg_984_DPTX(0x518,int(Port), Device_RX )
	print "REG_0518 (MST_ACTIVE_PAYLOAD_TABLE) = ", (REG_0518)

	REG_0520= apb_read_reg_984_DPTX(0x520,int(Port), Device_RX )
	print "REG_0520 (MST_ACTIVE) = ", (REG_0520)

	REG_0524= apb_read_reg_984_DPTX(0x524,int(Port), Device_RX )
	print "REG_0524 (MST_LINK_FRAME_COUNT) = ", (REG_0524)

	REG_0528= apb_read_reg_984_DPTX(0x528,int(Port), Device_RX )
	print "REG_0528 (MSO_CONFIGURATION) = ", (REG_0528)

	REG_0528= apb_read_reg_984_DPTX(0x528,int(Port), Device_RX )
	print "REG_0528 (MSO_CONFIGURATION) = ", (REG_0528)

	# Port = 1

	# print ""
	# print "PORT ",Port," DPTX APB Dump: Main Stream Attributes"
	# print ""

	# REG_000= apb_read_reg(0x000,int(Port), Device_RX )
	# print "REG_000 (LINK_BW_SET) = ", (REG_000)

	# REG_004= apb_read_reg(0x004,int(Port), Device_RX )
	# print "REG_004 (LANE_COUNT_SET) = ", (REG_004)

	# REG_008= apb_read_reg(0x008,int(Port), Device_RX )
	# print "REG_008 (ENHANCED_FRAME_EN) = ", (REG_008)

	# REG_00C= apb_read_reg(0x00C,int(Port), Device_RX )
	# print "REG_00C (TRAINING_PATTERN_SET) = ", (REG_00C)

	# REG_010= apb_read_reg(0x010,int(Port), Device_RX )
	# print "REG_010 (LINK_QUAL_PATTERN_SET) = ", (REG_010)

	# REG_014= apb_read_reg(0x014,int(Port), Device_RX )
	# print "REG_014 (SCRAMBLING_DISABLE) = ", (REG_014)

	# REG_018= apb_read_reg(0x018,int(Port), Device_RX )
	# print "REG_018 (DOWNSPREAD_CTRL) = ", (REG_018)

	# REG_01C= apb_read_reg(0x01C,int(Port), Device_RX )
	# print "REG_01C (EDP_CAPABILITY_CONFIG) = ", (REG_01C)

	# REG_020= apb_read_reg(0x020,int(Port), Device_RX )
	# print "REG_020 (HBR2_COMPLIANCE_SCRAMBLER_RESET) = ", (REG_020)

	# REG_024= apb_read_reg(0x024,int(Port), Device_RX )
	# print "REG_024 (DISPLAYPORT_VERSION) = ", (REG_024)

	# REG_028= apb_read_reg(0x028,int(Port), Device_RX )
	# print "REG_024 (PHY_POWER_STATE) = ", (REG_028)

	# REG_02C= apb_read_reg(0x02C,int(Port), Device_RX )
	# print "REG_02C (LANE_REMAP_CONTROL) = ", (REG_02C)

	# REG_030= apb_read_reg(0x030,int(Port), Device_RX )
	# print "REG_030 (CUSTOM_80BIT_PATTERN_0) = ", (REG_030)

	# REG_034= apb_read_reg(0x034,int(Port), Device_RX )
	# print "REG_034 (CUSTOM_80BIT_PATTERN_1) = ", (REG_034)

	# REG_038= apb_read_reg(0x038,int(Port), Device_RX )
	# print "REG_038 (CUSTOM_80BIT_PATTERN_2) = ", (REG_038)

	# REG_060= apb_read_reg(0x060,int(Port), Device_RX )
	# print "REG_060 (FEC_ENABLE) = ", (REG_060)

	# REG_080= apb_read_reg(0x080,int(Port), Device_RX )
	# print "REG_080 (TRANSMITTER_OUTPUT_ENABLE) = ", (REG_080)

	# REG_084= apb_read_reg(0x084,int(Port), Device_RX )
	# print "REG_084 (VIDEO_STREAM_ENABLE) = ", (REG_084)

	# REG_088= apb_read_reg(0x088,int(Port), Device_RX )
	# print "REG_088 (SECONDARY_STREAM_ENABLE) = ", (REG_088)

	# REG_08C= apb_read_reg(0x08C,int(Port), Device_RX )
	# print "REG_088 (SECONDARY_DATA_WINDOW) = ", (REG_08C)

	# REG_090= apb_read_reg(0x090,int(Port), Device_RX )
	# print "REG_090 (SOFT_RESET) = ", (REG_090)

	# REG_094= apb_read_reg(0x094,int(Port), Device_RX )
	# print "REG_094 (INPUT_SOURCE_ENABLE) = ", (REG_094)

	# REG_098= apb_read_reg(0x098,int(Port), Device_RX )
	# print "REG_098 (FEC_ENABLE) = ", (REG_098)

	# REG_0C0= apb_read_reg(0x0C0,int(Port), Device_RX )
	# print "REG_0C0 (ORCE_SCRAMBLER_RESET) = ", (REG_0C0)

	# REG_0C4= apb_read_reg(0x0C4,int(Port), Device_RX )
	# print "REG_0C4 (USER_CONTROL_STATUS) = ", (REG_0C4)

	# REG_0C8= apb_read_reg(0x0C8,int(Port), Device_RX )
	# print "REG_0C8 (USER_DATA_CONTROL) = ", (REG_0C8)

	# REG_0F8= apb_read_reg(0x0F8,int(Port), Device_RX )
	# print "REG_0F8 (CORE_CAPABILITIES) = ", (REG_0F8)

	# REG_0FC= apb_read_reg(0x0FC,int(Port), Device_RX )
	# print "REG_0FC (CORE_ID) = ", (REG_0FC)

	# REG_100= apb_read_reg(0x100,int(Port), Device_RX )
	# print "REG_100 (AUX_COMMAND) = ", (REG_100)

	# REG_104= apb_read_reg(0x104,int(Port), Device_RX )
	# print "REG_104 (AUX_WRITE_FIFO) = ", (REG_104)

	# REG_108= apb_read_reg(0x108,int(Port), Device_RX )
	# print "REG_108 (AUX_ADDRESS) = ", (REG_108)

	# REG_10C= apb_read_reg(0x10C,int(Port), Device_RX )
	# print "REG_10C (AUX_CLOCK_DIVIDER) = ", (REG_10C)

	# REG_110= apb_read_reg(0x110,int(Port), Device_RX )
	# print "REG_110 (AUX_REPLY_TIMEOUT_INTERVAL) = ", (REG_110)

	# REG_128= apb_read_reg(0x128,int(Port), Device_RX )
	# print "REG_128 (SINK_HPD_STATE) = ", (REG_128)

	# REG_130= apb_read_reg(0x130,int(Port), Device_RX )
	# print "REG_130 (INTERRUPT_STATE) = ", (REG_130)

	# REG_134= apb_read_reg(0x134,int(Port), Device_RX )
	# print "REG_134 (AUX_REPLY_DATA) = ", (REG_134)

	# REG_138= apb_read_reg(0x138,int(Port), Device_RX )
	# print "REG_138 (AUX_REPLY_CODE) = ", (REG_138)

	# REG_13C= apb_read_reg(0x13C,int(Port), Device_RX )
	# print "REG_13C (AUX_REPLY_COUNT) = ", (REG_13C)

	# REG_140= apb_read_reg(0x140,int(Port), Device_RX )
	# print "REG_140 (INTERRUPT_STATUS) = ", (REG_140)

	# REG_144= apb_read_reg(0x144,int(Port), Device_RX )
	# print "REG_144 (INTERRUPT_MASK) = ", (REG_144)

	# REG_148= apb_read_reg(0x148,int(Port), Device_RX )
	# print "REG_148 (REPLY_DATA_COUNT) = ", (REG_148)

	# REG_14C= apb_read_reg(0x14C,int(Port), Device_RX )
	# print "REG_14C (AUX_STATUS) = ", (REG_14C)

	# REG_150= apb_read_reg(0x150,int(Port), Device_RX )
	# print "REG_150 (AUX_REPLY_CLOCK_WIDTH) = ", (REG_150)

	# REG_154= apb_read_reg(0x154,int(Port), Device_RX )
	# print "REG_154 (AUX_WAKE_ACK_DETECTED) = ", (REG_154)

	# REG_158= apb_read_reg(0x158,int(Port), Device_RX )
	# print "REG_158 (GP_HOST_TIMER) = ", (REG_158)

	print ""
	print "STREAM: ", Stream, " Register Read: "
	print ""

	REG_0180= apb_read_reg_984_DPTX(0x180+Offset,int(Port), Device_RX )
	print "REG_0180 (MAIN_STREAM_HTOTAL) = ", (REG_0180)

	REG_0184= apb_read_reg_984_DPTX(0x184+Offset,int(Port), Device_RX )
	print "REG_0184 (MAIN_STREAM_VTOTAL) = ", (REG_0184)

	REG_0188= apb_read_reg_984_DPTX(0x188+Offset,int(Port), Device_RX )
	print "REG_0188 (MAIN_STREAM_POLARITY) = ", (REG_0188)

	REG_018C= apb_read_reg_984_DPTX(0x18C+Offset,int(Port), Device_RX )
	print "REG_018C (MAIN_STREAM_HSWIDTH) = ", (REG_018C)

	REG_0190= apb_read_reg_984_DPTX(0x190+Offset,int(Port), Device_RX )
	print "REG_0190 (MAIN_STREAM_VSWIDTH) = ", (REG_0190)

	REG_0194= apb_read_reg_984_DPTX(0x194+Offset,int(Port), Device_RX )
	print "REG_0194 (MAIN_STREAM_HRES) = ", (REG_0194)

	REG_0198= apb_read_reg_984_DPTX(0x198+Offset,int(Port), Device_RX )
	print "REG_0198 (MAIN_STREAM_VRES) = ", (REG_0198)

	REG_019C= apb_read_reg_984_DPTX(0x19C+Offset,int(Port), Device_RX )
	print "REG_019C (MAIN_STREAM_HSTART) = ", (REG_019C)

	REG_01A0= apb_read_reg_984_DPTX(0x1A0+Offset,int(Port), Device_RX )
	print "REG_01A0 (MAIN_STREAM_VSTART) = ", (REG_01A0)

	REG_01A4= apb_read_reg_984_DPTX(0x1A4+Offset,int(Port), Device_RX )
	print "REG_01A4 (MAIN_STREAM_MISC0) = ", (REG_01A4)

	REG_01A8= apb_read_reg_984_DPTX(0x1A8+Offset,int(Port), Device_RX )
	print "REG_01A8 (MAIN_STREAM_MISC1) = ", (REG_01A8)

	REG_01AC= apb_read_reg_984_DPTX(0x1AC+Offset,int(Port), Device_RX )
	print "REG_01AC (MVID) = ", (REG_01AC)

	REG_01B0= apb_read_reg_984_DPTX(0x1B0+Offset,int(Port), Device_RX )
	print "REG_01B0 (TRANSFER_UNIT_CONFIG_SRC_0) = ", (REG_01B0)

	REG_01B4= apb_read_reg_984_DPTX(0x1B4+Offset,int(Port), Device_RX )
	print "REG_01B4 (NVID) = ", (REG_01B4)

	REG_01B8= apb_read_reg_984_DPTX(0x1B8+Offset,int(Port), Device_RX )
	print "REG_01B8 (USER_PIXEL_COUNT) = ", (REG_01B8)

	REG_01BC= apb_read_reg_984_DPTX(0x1BC+Offset,int(Port), Device_RX )
	print "REG_01BC (USER_DATA_COUNT) = ", (REG_01BC)

	REG_01C0= apb_read_reg_984_DPTX(0x1C0+Offset,int(Port), Device_RX )
	print "REG_01C0 (MAIN_STREAM_INTERLACED) = ", (REG_01C0)

	REG_01C4= apb_read_reg_984_DPTX(0x1C4+Offset,int(Port), Device_RX )
	print "REG_01C4 (USER_SYNC_POLARITY) = ", (REG_01C4)

	REG_01C8= apb_read_reg_984_DPTX(0x1C8+Offset,int(Port), Device_RX )
	print "REG_01C8 (USER_CONTROL) = ", (REG_01C8)

	REG_0500= apb_read_reg_984_DPTX(0x500,int(Port), Device_RX )
	print "REG_0500 (MST_ENABLE) = ", (REG_0500)

	REG_0504= apb_read_reg_984_DPTX(0x504,int(Port), Device_RX )
	print "REG_0504 (MST_PID_TABLE_INDEX) = ", (REG_0504)

	REG_0508= apb_read_reg_984_DPTX(0x504,int(Port), Device_RX )
	print "REG_0508 (MST_PID_TABLE_ENTRY) = ", (REG_0508)

	REG_050C= apb_read_reg_984_DPTX(0x50C,int(Port), Device_RX )
	print "REG_050C (SST_SOURCE_SELECT) = ", (REG_050C)

	REG_0510= apb_read_reg_984_DPTX(0x510,int(Port), Device_RX )
	print "REG_0510 (MST_ALLOCATION_TRIGGER) = ", (REG_0510)

	REG_0514= apb_read_reg_984_DPTX(0x514,int(Port), Device_RX )
	print "REG_0514 (MST_PID_TABLE_SELECT) = ", (REG_0514)

	REG_0518= apb_read_reg_984_DPTX(0x518,int(Port), Device_RX )
	print "REG_0518 (MST_ACTIVE_PAYLOAD_TABLE) = ", (REG_0518)

	REG_0520= apb_read_reg_984_DPTX(0x520,int(Port), Device_RX )
	print "REG_0520 (MST_ACTIVE) = ", (REG_0520)

	REG_0524= apb_read_reg_984_DPTX(0x524,int(Port), Device_RX )
	print "REG_0524 (MST_LINK_FRAME_COUNT) = ", (REG_0524)

	REG_0528= apb_read_reg_984_DPTX(0x528,int(Port), Device_RX )
	print "REG_0528 (MSO_CONFIGURATION) = ", (REG_0528)

	REG_0528= apb_read_reg_984_DPTX(0x528,int(Port), Device_RX )
	print "REG_0528 (MSO_CONFIGURATION) = ", (REG_0528)

def Ux983_APBs(var): 
	for var in range (0x00,138):
		print hex(var*4), hex(apb_read_reg(serAddr,var*4))
		
	for var in range (256,336):
		print hex(var*4), hex(apb_read_reg(serAddr,var*4))
		
	for var in range (448,457):
		print hex(var*4), hex(apb_read_reg(serAddr,var*4))

	for var in range (512,589+1):
		print hex(var*4), hex(apb_read_reg(serAddr,var*4))
		
	for var in range (640,760+1):
		print hex(var*4), hex(apb_read_reg(serAddr,var*4))

def HH983_APBs():
	print("Receiver core config")
	print("0x0 (reciver core enable) = " + hex(apb_read_reg(serAddr,0x0)))
	print("0x018 (misc_config) = " + hex(apb_read_reg(serAddr,0x018)))
	print("0x024 (request_error_count) = " + hex(apb_read_reg(serAddr,0x024)))
	print("0x028 (request_count) = " + hex(apb_read_reg(serAddr,0x028)))
	print("0x070 (max_lane_count) = " + hex(apb_read_reg(serAddr,0x070)))
	print("0x074 (max_link_rate) = " + hex(apb_read_reg(serAddr,0x074)))
	print("")
	print("PHY config and status")
	print("0x208 (phy_status) = " + hex(apb_read_reg(serAddr,0x208)))
	print("0x214 (min_voltage_swing) = " + hex(apb_read_reg(serAddr,0x214)))
	print("0x218 (min_pre_emphasis) = " + hex(apb_read_reg(serAddr,0x218)))
	print("0x208 (phy_status) = " + hex(apb_read_reg(serAddr,0x208)))
	print("")
	print("DPCD config space")
	print("0x400 (LANE01_status) = " + hex(apb_read_reg(serAddr,0x400)))
	print("0x404 (LANE23_status) = " + hex(apb_read_reg(serAddr,0x404)))
	print("---MSA Video Timings----")
	print("H Res: ", apb_read_reg(serAddr,0x500))
	print("H Pol: ", apb_read_reg(serAddr,0x504))
	hsync = apb_read_reg(serAddr,0x508)
	print("H Sync: ", apb_read_reg(serAddr,0x508))
	print("H Back Porch: ", apb_read_reg(serAddr,0x50C) - hsync)
	print("H Total: ", apb_read_reg(serAddr,0x510))

	print("V Res: ", apb_read_reg(serAddr,0x514))
	print("V Pol: ", apb_read_reg(serAddr,0x518))

	v_sync = apb_read_reg(serAddr,0x51c)
	print("V Sync Width: ", v_sync)
	print("V Back Porch: ", apb_read_reg(serAddr,0x520) - v_sync)
	print("V Total: ", apb_read_reg(serAddr,0x524))
	print("    ")
	print("MSA MISC0: ", apb_read_reg(serAddr,0x528))
	print("MSA_MISC1: ", apb_read_reg(serAddr,0x52C))
	print("MSA_MVID: ", hex(apb_read_reg(serAddr,0x530)))
	print("MSA_NVID: ", hex(apb_read_reg(serAddr,0x534)))
	print("MSA_VBID: ", hex(apb_read_reg(serAddr,0x538)))
	print("MSA Updated", apb_read_reg(serAddr,0x544))
	print("")
	print("HDCP Config")
	print("0x600 (HDCP_enable) = " + hex(apb_read_reg(serAddr,0x600)))
	print("0x604 (HDCP_mode_select) = " + hex(apb_read_reg(serAddr,0x604)))
	# print("0x608 (HDCP_KS_31_0) = " + hex(apb_read_reg(serAddr,0x608)))
	# print("0x60C (HDCP_KS_63_32) = " + hex(apb_read_reg(serAddr,0x60C)))
	# print("0x610 (HDCP_KM_31_0) = " + hex(apb_read_reg(serAddr,0x610)))
	# print("0x614 (HDCP_KM_55_32) = " + hex(apb_read_reg(serAddr,0x614)))
	print("0x618 (HDCP_AN_31_0) = " + hex(apb_read_reg(serAddr,0x618)))
	print("0x61C (HDCP_AN_63_32) = " + hex(apb_read_reg(serAddr,0x61C)))
	print("0x624 (HDCP_authentication_in_progress) = " + hex(apb_read_reg(serAddr,0x624)))
	print("0x628 (HDCP_status) = " + hex(apb_read_reg(serAddr,0x628)))
	print("0x62C (HDCP_CIPHER_CONTROL) = " + hex(apb_read_reg(serAddr,0x62C)))
	print("0x630 (HDCP_AKSV_31_0) = " + hex(apb_read_reg(serAddr,0x630)))
	print("0x634 (HDCP_AKSV_63_32) = " + hex(apb_read_reg(serAddr,0x634)))
	print("0x638 (HDCP_HW_BKSV_31_0) = " + hex(apb_read_reg(serAddr,0x638)))
	print("0x63C (HDCP_HW_BKSV_63_32) = " + hex(apb_read_reg(serAddr,0x63C)))
	print("0x650 (HDCP_REPEATER) = " + hex(apb_read_reg(serAddr,0x650)))
	print("0x654 (HDCP_stream_cipher_enable) = " + hex(apb_read_reg(serAddr,0x654)))
	print("0x658 (HDCP_MO_31_0) = " + hex(apb_read_reg(serAddr,0x658)))
	print("0x65C (HDCP_MO_63_32) = " + hex(apb_read_reg(serAddr,0x65C)))
	print("0x660 (HDCP_AES_INPUT_SELECT) = " + hex(apb_read_reg(serAddr,0x660)))
	print("0x664 (HDCP_AES_COUNTER_DISABLE) = " + hex(apb_read_reg(serAddr,0x664)))
	print("0x668 (HDCP_AES_COUNTER_ADVANCE) = " + hex(apb_read_reg(serAddr,0x668)))
	print("0x66C (HDCP_ENCRYPTION_CONTROL_FIELD_31_0) = " + hex(apb_read_reg(serAddr,0x66C)))
	print("0x670 (HDCP_ENCRYPTION_CONTROL_FIELD_63_32) = " + hex(apb_read_reg(serAddr,0x670)))
	print("0x678 (HDCP_RN_31_0) = " + hex(apb_read_reg(serAddr,0x678)))
	print("0x67C (HDCP_RN_63_32) = " + hex(apb_read_reg(serAddr,0x67C)))
	print("0x684 (HDCP_RNG_CIPHER_AN_31_0) = " + hex(apb_read_reg(serAddr,0x684)))
	print("0x688 (HDCP_RNG_CIPHER_AN_63_32) = " + hex(apb_read_reg(serAddr,0x688)))
	print("0x68C (HDCP_HOST_TIMER) = " + hex(apb_read_reg(serAddr,0x68C)))
	print("0x690 (HDCP_encryption_active) = " + hex(apb_read_reg(serAddr,0x690)))
	print("0x694 (HDCP_link_integrity_failure) = " + hex(apb_read_reg(serAddr,0x694)))
	print("0x698 (HDCP_content_type_select_31_0) = " + hex(apb_read_reg(serAddr,0x698)))
	print("0x69C (HDCP_content_type_select_63_32) = " + hex(apb_read_reg(serAddr,0x69C)))

def Ux948_Res_dump(desAlias0):
	time.sleep(1)
	board.WriteI2C(desAlias0,0x68,0x19) # H active High monitor
	Hhigh = board.ReadI2C(desAlias0, 0x69, 1)
	board.WriteI2C(desAlias0,0x68,0x09) # H active Low monitor
	Hlow = board.ReadI2C(desAlias0, 0x69, 1)
	board.WriteI2C(desAlias0,0x68,0x39) # V active High monitor
	Vhigh = board.ReadI2C(desAlias0, 0x69, 1)
	board.WriteI2C(desAlias0,0x68,0x29) # V active Low monitor
	Vlow = board.ReadI2C(desAlias0, 0x69, 1)
	mask = int('00111111',2)
	hlowmask = Hlow & mask
	hhighmask = Hhigh & mask
	vlowmask = Vlow & mask
	vhighmask = Vhigh & mask
	hhighmask = hhighmask << 6
	vhighmask = vhighmask << 6
	Hactive = hhighmask | hlowmask
	Vactive = vhighmask | vlowmask
	print Hactive ,"x", Vactive ,",", #print out detected Dimensions

def Ux98x_SERDES_Full_Diagnostics():
	time.sleep(0.1)
	if SER == "HH983" or SER == "Ux983" or SER == "Ux943A":
		board.WriteI2C(serAddr, 0x7, 0x88)  # Enable I2C Passthrough for FPD4 98x SER

	if SER == "Hx94x":
		board.WriteI2C(serAddr, 0x3, 0xDA)  # Enable I2C Passthrough for FPD4 98x SER



	if SER == "Ux94x":
		print"Ux94x Statuses"
		for x in range(20):
			print"Device_ID = ", hex(board.ReadI2C(serAddr, 0x0)), ",",
			print"GENERAL_STATUS = ", hex(board.ReadI2C(serAddr, 0xC))

			# Clear CRC Erorr"
			Reg_4 = board.ReadI2C(serAddr, 0x4)
			Reg_4_mask = Reg_4 | 0x20
			board.WriteI2C(serAddr, 0x4, Reg_4_mask)  # CRC Error Reset

		Reg_4 = board.ReadI2C(serAddr, 0x4)
		Reg_4_unmask = Reg_4 & 0xDF
		board.WriteI2C(serAddr, 0x4, Reg_4_unmask)  # CRC Error Reset Clear

		for x in range(20):
			print"CRC_0xA = ", hex(board.ReadI2C(serAddr, 0xA)), ",",
			print"CRC_0xB = ", hex(board.ReadI2C(serAddr, 0xB))


	if DES == "Ux948":
		print "Ux948 Statuses"
		for x in range(20):
			print"GENERAL_STATUS = ", hex(board.ReadI2C(desAlias0, 0x1C)), ",",
			print"DUAL_RX_CTL = ", hex(board.ReadI2C(desAlias0, 0x34)), ",",
			print"Mode_Sel = ", hex(board.ReadI2C(desAlias0, 0x37)), ",",
			Ux948_Res_dump(desAlias0)
			print"FPD_TX_MODE = ", hex(board.ReadI2C(desAlias0, 0x49))


	if SER == "HH983" or SER == "Ux983" or SER == "Ux943A" or SER == "Ux981":
		print"----------------------------------"
		print("Lock / Link Status")
		for x in range(10):
			print"Ser Reg 0xC = ", hex(board.ReadI2C(serAddr, 0xC, 1)), ",",
			print"Des Reg 0x53 = ", hex(board.ReadI2C(desAlias0, 0x53, 1)), ",",
			print"Des Reg 0x54 = ", hex(board.ReadI2C(desAlias0, 0x54, 1)), ",",
			board.WriteI2C(serAddr, 0x40, 18 * 4 + 1)
			board.WriteI2C(serAddr, 0x41, 0x4E)
			print"Des Reg 0x4E = ", hex(board.ReadI2C(desAlias0, 0x42))


	if VP and SER == "HH983" or SER == "Ux983" or SER == "Ux943A" or SER == "Ux981":
		print "----------------------------------"
		print ("VP Status")
		for x in range(10):
			board.WriteI2C(serAddr, 0x40, 0x33)
			board.WriteI2C(serAddr, 0x41, 0x30)
			print "VP_STATUS:", board.ReadI2C(serAddr, 0x42, 1), ",",

			board.WriteI2C(serAddr, 0x40, 0x33)
			board.WriteI2C(serAddr, 0x41, 0x31)
			print "VP_INTERRUPTS:", board.ReadI2C(serAddr, 0x42, 1)



	if SER == "Ux981":
		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0xe)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"INTR_STS_DPHY = 0x", hex(read_val)
		print"[1] IS_DPHY_LANE_SYNC_ERROR", (read_val & 0x2) >> 1
		print"[0] IS_DPHY_LANE_ERROR", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0xf)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_STATUS = 0x", hex(read_val)
		print"[4] C_LANE_ACTIVE", (read_val & 0x10) >> 4
		print"[3] D_LANE3_ACTIVE", (read_val & 0x8) >> 3
		print"[2] D_LANE2_ACTIVE", (read_val & 0x4) >> 2
		print"[1] D_LANE1_ACTIVE", (read_val & 0x2) >> 1
		print"[0] D_LANE0_ACTIVE", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x10)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_DLANE0 = 0x", hex(read_val)
		print"[4] EOT_SYNC_ERROR", (read_val & 0x10) >> 4
		print"[3] SOT_ERROR", (read_val & 0x8) >> 3
		print"[2] SOT_SYNC_ERROR", (read_val & 0x4) >> 2
		print"[1] CNTRL_ERR_HSRQST", (read_val & 0x2) >> 1
		print"[0] HS_RX_TO_ERROR", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x11)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_DLANE1 = 0x", hex(read_val)
		print"[4] EOT_SYNC_ERROR", (read_val & 0x10) >> 4
		print"[3] SOT_ERROR", (read_val & 0x8) >> 3
		print"[2] SOT_SYNC_ERROR", (read_val & 0x4) >> 2
		print"[1] CNTRL_ERR_HSRQST", (read_val & 0x2) >> 1
		print"[0] HS_RX_TO_ERROR", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x12)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_DLANE2 = 0x", hex(read_val)
		print"[4] EOT_SYNC_ERROR", (read_val & 0x10) >> 4
		print"[3] SOT_ERROR", (read_val & 0x8) >> 3
		print"[2] SOT_SYNC_ERROR", (read_val & 0x4) >> 2
		print"[1] CNTRL_ERR_HSRQST", (read_val & 0x2) >> 1
		print"[0] HS_RX_TO_ERROR", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x13)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_DLANE3 = 0x", hex(read_val)
		print"[4] EOT_SYNC_ERROR", (read_val & 0x10) >> 4
		print"[3] SOT_ERROR", (read_val & 0x8) >> 3
		print"[2] SOT_SYNC_ERROR", (read_val & 0x4) >> 2
		print"[1] CNTRL_ERR_HSRQST", (read_val & 0x2) >> 1
		print"[0] HS_RX_TO_ERROR", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x14)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_ERR_CLK_LANE = 0x", hex(read_val)
		print
		"[2] CNTRL_ERR_HSRQST_CLK", (read_val & 0x4) >> 2
		print"[0] HS RX TO ERROR_CLK", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x15)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_SYNC_STS = 0x", read_val
		print"[3] DLANE3_SYNC_STS", (read_val & 0x8) >> 3
		print"[2] DLANE2_SYNC_STS", (read_val & 0x4) >> 2
		print"[1] DLANE1_SYNC_STS", (read_val & 0x2) >> 1
		print"[0] DLANE0_SYNC_STS", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x23)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"INTR_STS_DSI_ERR = 0x", read_val
		print"[7] IS_INV_TYPE_GLW_ERR", (read_val & 0x80) >> 7
		print"[6] IS_INV_WC_GLW_ERR", (read_val & 0x40) >> 6
		print"[5] IS_INV_LEN_ERR", (read_val & 0x20) >> 5
		print"[4] IS_INV_VC_ERR", (read_val & 0x10) >> 4
		print"[3] IS_INV_DT_ERR", (read_val & 0x8) >> 3
		print"[2] IS_CHECKSUM_ERR", (read_val & 0x4) >> 2
		print"[1] IS_ECC_MULTI_ERR", (read_val & 0x2) >> 1
		print"[0] IS_ECC_SINGLE_ERR", read_val & 0x1

		board.WriteI2C(serAddr, 0x40, 4 * 4 + 1)
		board.WriteI2C(serAddr, 0x41, 0x2a)
		read_val = board.ReadI2C(serAddr, 0x42)
		print"DPHY_DSI_VC_DTYPE = 0x", read_val




	if SER == "HH983" and DPRX:
		print "----------------------------------"
		print ("DPRX Status")
		apb_write_reg(serAddr, 0x4F4, 0x00)  # Address [19:16]
		apb_write_reg(serAddr, 0x4F0, 0x03)
		apb_write_reg(serAddr, 0x4F4, 0x01)  # Address [15:8]
		apb_write_reg(serAddr, 0x4F0, 0x03)
		apb_write_reg(serAddr, 0x4F4, 0x00)  # Address [7:0]
		apb_write_reg(serAddr, 0x4F0, 0x03)
		apb_write_reg(serAddr, 0x4F0, 0x02)  # Read Strobe
		LINK_BW_SET = apb_read_reg(serAddr, 0x4F8)
		if LINK_BW_SET == 0:
			print "No Link Speed Detected"
		elif LINK_BW_SET == 0x06:
			print "Link Rate = 1.62Gbps/lane"
		elif LINK_BW_SET == 0x0A:
			print "Link Rate = 2.7Gbps/lane"
		elif LINK_BW_SET == 0x14:
			print "Link Rate = 5.4Gbps/lane"
		elif LINK_BW_SET == 0x1E:
			print "Link Rate = 8.1Gbps/lane"

		# Lane Count Check via Direct DPCD Access
		apb_write_reg(serAddr, 0x4F4, 0x00)  # Address [19:16]
		apb_write_reg(serAddr, 0x4F0, 0x03)
		apb_write_reg(serAddr, 0x4F4, 0x01)  # Address [15:8]
		apb_write_reg(serAddr, 0x4F0, 0x03)
		apb_write_reg(serAddr, 0x4F4, 0x01)  # Address [7:0]
		apb_write_reg(serAddr, 0x4F0, 0x03)
		apb_write_reg(serAddr, 0x4F0, 0x02)  # Read Strobe
		LANE_COUNT_SET = apb_read_reg(serAddr, 0x4F8)
		if LANE_COUNT_SET & 0x1F == 0:
			print "No Active DP Lanes Detected"
		elif LANE_COUNT_SET & 0x1F == 0x01:
			print "One DP Lane"
		elif LANE_COUNT_SET & 0x1F == 0x02:
			print "Two DP Lanes"
		elif LANE_COUNT_SET & 0x1F == 0x04:
			print "4 DP Lanes"

		print("H Res")
		print apb_read_reg(serAddr, 0x500)

		print("H POL")
		print apb_read_reg(serAddr, 0x504)

		print("H SYNC WIDTH")
		h_sync = apb_read_reg(serAddr, 0x508)
		print h_sync

		print("H BACK PORCH")
		H_Back = apb_read_reg(serAddr, 0x50C) - h_sync
		print H_Back

		print("H TOTAL")
		print apb_read_reg(serAddr, 0x510)

		print("V Res")
		print apb_read_reg(serAddr, 0x514)

		print("V POL")
		print apb_read_reg(serAddr, 0x518)

		print("V SYNC WIDTH")
		v_sync = apb_read_reg(serAddr, 0x51C)
		print v_sync

		print("V BACK PORCH ")
		v_back = apb_read_reg(serAddr, 0x520) - v_sync
		print v_back

		print("HV TOTAL")
		print apb_read_reg(serAddr, 0x524)

		print("MSA_MISC0")
		print apb_read_reg(serAddr, 0x528)

		print("MSA_MISC1")
		print apb_read_reg(serAddr, 0x52C)

		print("MSA_MVID")
		print apb_read_reg(serAddr, 0x530)

		print("MSA_NVID")
		print apb_read_reg(serAddr, 0x534)

		print("MSA_VBID")
		print apb_read_reg(serAddr, 0x538)

	if SER == "Ux983" or SER == "Ux943A":
		print "----------------------------------"
		print ("DPRX Status")
		print apb_read_reg(serAddr, 0x400) * 27, ("Rate")
		print apb_read_reg(serAddr, 0x404), ("Lanes")
		print hex(apb_read_reg(serAddr, 0x43c))
		print hex(apb_read_reg(serAddr, 0x440))
		print hex(apb_read_reg(serAddr, 0x18))
		print hex(apb_read_reg(serAddr, 0x48C))
		if apb_read_reg(serAddr, 0x48C) == 0:
			print "Video source is set to SST mode"
		if apb_read_reg(serAddr, 0x48C) == 1:
			print "Video source is set to MST mode"
		print "----------------------------------"

		if SER == "Ux983" or SER ==  "Ux943A" and SER_MSAs:
			if MST == 0:
				apb_write_reg(serAddr, 0x540, 0x0)
				print("H Res")
				print apb_read_reg(serAddr, 0x500)

				print("H POL")
				print apb_read_reg(serAddr, 0x504)

				print("H SYNC WIDTH")
				h_sync = apb_read_reg(serAddr, 0x508)
				print h_sync

				print("H BACK PORCH")
				H_Back = apb_read_reg(serAddr, 0x50C) - h_sync
				print H_Back

				print("H TOTAL")
				print apb_read_reg(serAddr, 0x510)

				print("V Res")
				print apb_read_reg(serAddr, 0x514)

				print("V POL")
				print apb_read_reg(serAddr, 0x518)

				print("V SYNC WIDTH")
				v_sync = apb_read_reg(serAddr, 0x51C)
				print v_sync

				print("V BACK PORCH ")
				v_back = apb_read_reg(serAddr, 0x520) - v_sync
				print v_back

				print("HV TOTAL")
				print apb_read_reg(serAddr, 0x524)

				print("MSA_MISC0")
				print apb_read_reg(serAddr, 0x528)

				print("MSA_MISC1")
				print apb_read_reg(serAddr, 0x52C)

				print("MSA_MVID")
				print apb_read_reg(serAddr, 0x530)

				print("MSA_NVID")
				print apb_read_reg(serAddr, 0x534)

				print("MSA_VBID")
				print apb_read_reg(serAddr, 0x538)

				print("SYMBOL ERRORs - Lane 0")
				print hex(apb_read_reg(serAddr, 0x490))

				print("SYMBOL ERRORs - Lane 1")
				print hex(apb_read_reg(serAddr, 0x494))

				print("SYMBOL ERRORs - Lane 2")
				print hex(apb_read_reg(serAddr, 0x498))

				print("SYMBOL ERRORs - Lane 3")
				print hex(apb_read_reg(serAddr, 0x49C))

			else:
				print "----------------------------------"
				print("## MST0")
				apb_write_reg(serAddr, 0x540, 0x0)
				print("H Res")
				print apb_read_reg(serAddr, 0x500)

				print("H POL")
				print apb_read_reg(serAddr, 0x504)

				print("H SYNC WIDTH")
				h_sync = apb_read_reg(serAddr, 0x508)
				print h_sync

				print("H BACK PORCH")
				H_Back = apb_read_reg(serAddr, 0x50C) - h_sync
				print H_Back

				print("H TOTAL")
				print apb_read_reg(serAddr, 0x510)

				print("V Res")
				print apb_read_reg(serAddr, 0x514)

				print("V POL")
				print apb_read_reg(serAddr, 0x518)

				print("V SYNC WIDTH")
				v_sync = apb_read_reg(serAddr, 0x51C)
				print v_sync

				print("V BACK PORCH ")
				v_back = apb_read_reg(serAddr, 0x520) - v_sync
				print v_back

				print("HV TOTAL")
				print apb_read_reg(serAddr, 0x524)

				print("MSA_MISC0")
				print apb_read_reg(serAddr, 0x528)

				print("MSA_MISC1")
				print apb_read_reg(serAddr, 0x52C)

				print("MSA_MVID")
				print apb_read_reg(serAddr, 0x530)

				print("MSA_NVID")
				print apb_read_reg(serAddr, 0x534)

				print("MSA_VBID")
				print apb_read_reg(serAddr, 0x538)

				print("SYMBOL ERRORs - Lane 0")
				print hex(apb_read_reg(serAddr, 0x490))

				print("SYMBOL ERRORs - Lane 1")
				print hex(apb_read_reg(serAddr, 0x494))

				print("SYMBOL ERRORs - Lane 2")
				print hex(apb_read_reg(serAddr, 0x498))

				print("SYMBOL ERRORs - Lane 3")
				print hex(apb_read_reg(serAddr, 0x49C))

				print("## MST1")
				apb_write_reg(serAddr, 0x540, 0x1)
				print("H Res")
				print apb_read_reg(serAddr, 0x500)

				print("H POL")
				print apb_read_reg(serAddr, 0x504)

				print("H SYNC WIDTH")
				h_sync = apb_read_reg(serAddr, 0x508)
				print h_sync

				print("H BACK PORCH")
				H_Back = apb_read_reg(serAddr, 0x50C) - h_sync
				print H_Back

				print("H TOTAL")
				print apb_read_reg(serAddr, 0x510)

				print("V Res")
				print apb_read_reg(serAddr, 0x514)

				print("V POL")
				print apb_read_reg(serAddr, 0x518)

				print("V SYNC WIDTH")
				v_sync = apb_read_reg(serAddr, 0x51C)
				print v_sync

				print("V BACK PORCH ")
				v_back = apb_read_reg(serAddr, 0x520) - v_sync
				print v_back

				print("HV TOTAL")
				print apb_read_reg(serAddr, 0x524)

				print("MSA_MISC0")
				print apb_read_reg(serAddr, 0x528)

				print("MSA_MISC1")
				print apb_read_reg(serAddr, 0x52C)

				print("MSA_MVID")
				print apb_read_reg(serAddr, 0x530)

				print("MSA_NVID")
				print apb_read_reg(serAddr, 0x534)

				print("MSA_VBID")
				print apb_read_reg(serAddr, 0x538)

				print("SYMBOL ERRORs - Lane 0")
				print hex(apb_read_reg(serAddr, 0x490))

				print("SYMBOL ERRORs - Lane 1")
				print hex(apb_read_reg(serAddr, 0x494))

				print("SYMBOL ERRORs - Lane 2")
				print hex(apb_read_reg(serAddr, 0x498))

				print("SYMBOL ERRORs - Lane 3")
				print hex(apb_read_reg(serAddr, 0x49C))

	if DES == "Ux984" or DES == "HH984":
		if DPTX:
			print "----------------------------------"
			print "DPTX Status"
			## AUX DP/eDP Train Status Read 0x202 and 0x203
			board.WriteI2C(desAlias0, 0x40, 0x2D)
			board.WriteI2C(desAlias0, 0x41, 0x93)
			print "Page11 reg 0x93 = ", hex(board.ReadI2C(desAlias0, 0x42, 1))
			for dpcdAddr in range(0x202, 0x204):
				apb_write_reg(desAlias0, 0x13C, 0x1)  # Clear AUX_Reply Count
				# Aux read transaction to read DPCD registers
				apb_write_reg(desAlias0, 0x108, dpcdAddr)  # aux address
				apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
				time.sleep(0.25)
				AUX_REPLY_COUNT = apb_read_reg(desAlias0, 0x13C)
				# print "AUX Reply Count:", AUX_REPLY_COUNT
				if AUX_REPLY_COUNT == 1:
					replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
					print "DPCD addr " + hex(dpcdAddr) + " is " + hex(replyData)
				else:
					print "No AUX Reply Detected"
					apb_write_reg(desAlias0, 0x108, 0x202)  # aux address
					apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
					time.sleep(0.25)
					replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
					apb_write_reg(desAlias0, 0x108, 0x202)  # aux address
					apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
					time.sleep(0.25)
					replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
					print "'DPCD addr " + hex(0x202) + " is " + hex(replyData)

					apb_write_reg(desAlias0, 0x108, 0x203)  # aux address
					apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
					time.sleep(0.25)
					replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
					apb_write_reg(desAlias0, 0x108, 0x203)  # aux address
					apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
					time.sleep(0.25)
					replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
					print "'DPCD addr " + hex(0x203) + " is " + hex(replyData)

			for dpcdAddr in range(0x100, 0x101):
				# Aux read transaction to read DPCD registers
				apb_write_reg(desAlias0, 0x108, dpcdAddr)  # aux address
				apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
				time.sleep(0.25)
				replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
				print "DPCD addr " + hex(dpcdAddr) + " is " + hex(replyData)
				if replyData == 10:
					print "DPTX = 2.7 Gbps"
				if replyData == 6:
					print "DPTX = 1.62 Gbps"
				if replyData == 20:
					print "DPTX = 5.4 Gbps"
				if replyData == 30:
					print "DPTX = 8.1 Gbps"

			for dpcdAddr in range(0x101, 0x102):
				# Aux read transaction to read DPCD registers
				apb_write_reg(desAlias0, 0x108, dpcdAddr)  # aux address
				apb_write_reg(desAlias0, 0x100, 0x900)  # aux Command to read
				time.sleep(0.25)
				replyData = apb_read_reg(desAlias0, 0x134)  # Read reply data
				print "DPCD addr " + hex(dpcdAddr) + " is " + hex(replyData)
				if replyData == 0x84:
					print "DP_Lanes = 4"
		print "----------------------------------"
		print "Des FIFO = ", hex(apb_read_reg(desAlias0, 0x1CC))

		if DTGs:
			print "----------------------------------"
			print "DTG Port 0 Timing:"
			measure = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]

			board.WriteI2C(desAlias0, 0x40, 0x53)
			board.WriteI2C(desAlias0, 0x41, 0x40)
			for x in range(0, 16, 1):
				measure[x] = board.ReadI2C(desAlias0, 0x42, 1)

			Htotal = (measure[0] << 8) | measure[1]
			print "Htotal = ", Htotal
			Vtotal = (measure[2] << 8) | measure[3]
			print "Vtotal = ", Vtotal
			Hactive = (measure[4] << 8) | measure[5]
			print "Hactive = ", Hactive
			Vactive = (measure[6] << 8) | measure[7]
			print "Vactive = ", Vactive
			Hstart = (measure[8] << 8) | measure[9]
			print "Hstart = ", Hstart
			Vstart = (measure[10] << 8) | measure[11]
			Hsync = (measure[12] << 8) | measure[13]
			print "Hsync = ", Hsync
			Vsync = (measure[14] << 8) | measure[15]
			print "Vsync = ", Vsync

			Vback = Vstart - Vsync
			print "Vback = ", Vback

			Vfront = Vtotal - Vactive - Vsync - Vback
			print "Vfront = ", Vfront

		if DP0 and DES == "Ux984":
			print "----------------------------------"
			print "Print Des MSAs"
			Measure_Video_DPTX(desAlias0, 0, 1)
			print "----------------------------------"
			print "Ux984 DPTX APBs"
			Ux984_APB_Dump(0,desAlias0)
		if DP0 and DES == "HH984":
			print "----------------------------------"
			print "Print Des MSAs"
			Measure_Video_DPTX_HH(desAlias0, 0, 1)

		if DP1 and DES == "Ux984":
			print "----------------------------------"
			print "Print Des MSAs"
			Measure_Video_DPTX(desAlias0, 1, 1)
		if DP1 and DES == "HH984":
			print "----------------------------------"
			print "Print Des MSAs"
			Measure_Video_DPTX_HH(desAlias0, 1, 1)
	if DES == "Ux988" :
		print "----------------------------------"
		print "Ux988 Status"
		print "DES_Addr = ", hex(board.ReadI2C(desAlias0, 0x0))
		for x in range(10):
			# print ("Link and Lock Status")
			print "Ser Reg 0xC = ", hex(board.ReadI2C(serAddr, 0xC, 1)), ",",
			print "Des Reg 0x53 = ", hex(board.ReadI2C(desAlias0, 0x53, 1)), ",",
			print "Des Reg 0x54 = ", hex(board.ReadI2C(desAlias0, 0x54, 1)), ",",
			board.WriteI2C(serAddr, 0x40, 18 * 4 + 1)
			board.WriteI2C(serAddr, 0x41, 0x4E)
			print "Des Reg 0x4E = ", hex(board.ReadI2C(desAlias0, 0x42))


		measure = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]

		board.WriteI2C(desAlias0, 0x40, 0x53)
		board.WriteI2C(desAlias0, 0x41, 0x40)
		for x in range(0, 16, 1):
			measure[x] = board.ReadI2C(desAlias0, 0x42, 1)
		print "----------------------------------"
		print "Ux988 DTGs"
		Htotal = (measure[0] << 8) | measure[1]
		print "Htotal = ", Htotal
		Vtotal = (measure[2] << 8) | measure[3]
		print "Vtotal = ", Vtotal
		Hactive = (measure[4] << 8) | measure[5]
		print "Hactive = ", Hactive
		Vactive = (measure[6] << 8) | measure[7]
		print "Vactive = ", Vactive
		Hstart = (measure[8] << 8) | measure[9]
		print "Hstart = ", Hstart
		Vstart = (measure[10] << 8) | measure[11]
		Hsync = (measure[12] << 8) | measure[13]
		print "Hsync = ", Hsync
		Vsync = (measure[14] << 8) | measure[15]
		print "Vsync = ", Vsync

		Vback = Vstart - Vsync
		print "Vback = ", Vback

		Vfront = Vtotal - Vactive - Vsync - Vback
		print "Vfront = ", Vfront
		board.WriteI2C(desAlias0, 0x41, 0x70)

		board.WriteI2C(desAlias0, 0x41, 0xA0)

		print "FPD IV Link Layer Timing:"

		board.WriteI2C(desAlias0, 0x40, 0x4B)
		board.WriteI2C(desAlias0, 0x41, 0x39)

		for x in range(0, 12, 1):
			measure[x] = board.ReadI2C(desAlias0, 0x42)

		Stream0 = (measure[1] << 8) | measure[0]
		Stream1 = (measure[3] << 8) | measure[2]
		Stream2 = (measure[5] << 8) | measure[4]
		Stream3 = (measure[7] << 8) | measure[6]
		Stream4 = (measure[9] << 8) | measure[8]
		Stream5 = (measure[11] << 8) | measure[10]

		print "Stream 0 Hactive = ", Stream0
		print "Stream 1 Hactive = ", Stream1
		print "Stream 2 Hactive = ", Stream2
		print "Stream 3 Hactive = ", Stream3
		print "Stream 4 Hactive = ", Stream4
		print "Stream 5 Hactive = ", Stream5

	if SER == "Ux983":
		print "-------------------------"
		print "Ux983_APB_dump"
		Ux983_APBs(0)

	if SER == "HH983":
		print "-------------------------"
		print "HH983_APB_dump"
		HH983_APBs()








Ux98x_SERDES_Full_Diagnostics()
time.sleep(0.1)

0 Ryan yan 6 天前回复 Links

Prodigy 40 points

一级供应商是合微健创，新的设计，串行器是DS90UB983-Q1、解串器是SNLS607A_DS90UB984-Q1，FPD-Link Ⅳ模式，屏幕参数如图所示，24位色深，现在还未调通，使用984打pattern屏幕能出图，证明984到屏幕的链路是通的，但983打pattern，屏幕未出图。是在室温开发板上测试的。已正确将视频流映射到DP1，因为984打pattern就是配置的DP1，DP信号设置的4lane和2.7G速率下面是您提供的脚本记录故障模式发生时的情况

Lock / Link Status
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x5
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x5
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0x2c , Des Reg 0x4E =  0x5
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x5
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x5
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x5
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x5
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x5
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x5
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x5
----------------------------------
VP Status
VP_STATUS: 12 , VP_INTERRUPTS: 17
VP_STATUS: 1 , VP_INTERRUPTS: 16
VP_STATUS: 1 , VP_INTERRUPTS: 16
VP_STATUS: 12 , VP_INTERRUPTS: 16
VP_STATUS: 1 , VP_INTERRUPTS: 16
VP_STATUS: 1 , VP_INTERRUPTS: 16
VP_STATUS: 1 , VP_INTERRUPTS: 16
VP_STATUS: 1 , VP_INTERRUPTS: 16
VP_STATUS: 1 , VP_INTERRUPTS: 16
VP_STATUS: 1 , VP_INTERRUPTS: 16
----------------------------------
DPRX Status
810 Rate
4 Lanes
0x30044
0x30044
0x4
0x0
Video source is set to SST mode
----------------------------------
H Res
0
H POL
0
H SYNC WIDTH
0
H BACK PORCH
0
H TOTAL
0
V Res
0
V POL
0
V SYNC WIDTH
0
V BACK PORCH
0
HV TOTAL
0
MSA_MISC0
0
MSA_MISC1
0
MSA_MVID
0
MSA_NVID
0
MSA_VBID
25
SYMBOL ERRORs - Lane 0
0x80000000L
SYMBOL ERRORs - Lane 1
0x80000000L
SYMBOL ERRORs - Lane 2
0x80000000L
SYMBOL ERRORs - Lane 3
0x80000000L
----------------------------------
DPTX Status
Page11 reg 0x93 =  0x0
No AUX Reply Detected
'DPCD addr 0x202 is 0xf4
'DPCD addr 0x203 is 0xa7
No AUX Reply Detected
'DPCD addr 0x202 is 0x83
'DPCD addr 0x203 is 0xf5
DPCD addr 0x100 is 0xfb
DPCD addr 0x101 is 0x66
----------------------------------
Des FIFO =  0x0
----------------------------------
DTG Port 0 Timing:
Htotal =  0
Vtotal =  0
Hactive =  11358
Vactive =  0
Hstart =  0
Hsync =  0
Vsync =  0
Vback =  0
Vfront =  0
----------------------------------
Print Des MSAs

('Port', 0, ': DPTX VIDEO RESOLUTION:')
('Port', 0, ': htotal (0x180) = 0')
('Port', 0, ': vtotal (0x184) = 0')
('Port', 0, ': hres (0x18C) = 0')
('Port', 0, ': vres (0x190) = 0')
('Port', 0, ': hstart (0x19C) = 0')
('Port', 0, ': vstart (0x1A0) = 0')
('Port', 0, ': hswidth (0x18C) = 0')
('Port', 0, ': vswidth (0x18C) = 0')
----------------------------------
Ux984 DPTX APBs
PORT  0  DPTX APB Dump: Main Stream Attributes
REG_000 (LINK_BW_SET) =  0
REG_004 (LANE_COUNT_SET) =  0
REG_008 (ENHANCED_FRAME_EN) =  1
REG_00C (TRAINING_PATTERN_SET) =  0
REG_010 (LINK_QUAL_PATTERN_SET) =  0
REG_014 (SCRAMBLING_DISABLE) =  44
REG_018 (DOWNSPREAD_CTRL) =  0
REG_01C (EDP_CAPABILITY_CONFIG) =  0
REG_020 (HBR2_COMPLIANCE_SCRAMBLER_RESET) =  0
REG_024 (DISPLAYPORT_VERSION) =  18
REG_024 (PHY_POWER_STATE) =  0
REG_02C (LANE_REMAP_CONTROL) =  0
REG_030 (CUSTOM_80BIT_PATTERN_0) =  0
REG_034 (CUSTOM_80BIT_PATTERN_1) =  0
REG_038 (CUSTOM_80BIT_PATTERN_2) =  0
REG_060 (FEC_ENABLE) =  0
REG_080 (TRANSMITTER_OUTPUT_ENABLE) =  0
REG_084 (VIDEO_STREAM_ENABLE) =  0
REG_088 (SECONDARY_STREAM_ENABLE) =  0
REG_088 (SECONDARY_DATA_WINDOW) =  128
REG_090 (SOFT_RESET) =  0
REG_094 (INPUT_SOURCE_ENABLE) =  0
REG_098 (FEC_ENABLE) =  0
REG_0C0 (ORCE_SCRAMBLER_RESET) =  44
REG_0C4 (USER_CONTROL_STATUS) =  0
REG_0C8 (USER_DATA_CONTROL) =  537141252
REG_0F8 (CORE_CAPABILITIES) =  5636
REG_0FC (CORE_ID) =  656648
REG_100 (AUX_COMMAND) =  2304
REG_104 (AUX_WRITE_FIFO) =  0
REG_108 (AUX_ADDRESS) =  257
REG_10C (AUX_CLOCK_DIVIDER) =  0
REG_110 (AUX_REPLY_TIMEOUT_INTERVAL) =  400
REG_128 (SINK_HPD_STATE) =  0
REG_130 (INTERRUPT_STATE) =  0
REG_134 (AUX_REPLY_DATA) =  66
REG_138 (AUX_REPLY_CODE) =  0
REG_13C (AUX_REPLY_COUNT) =  738197504
REG_140 (INTERRUPT_STATUS) =  0
REG_144 (INTERRUPT_MASK) =  63
REG_148 (REPLY_DATA_COUNT) =  0
REG_14C (AUX_STATUS) =  20
REG_150 (AUX_REPLY_CLOCK_WIDTH) =  0
REG_154 (AUX_WAKE_ACK_DETECTED) =  0
REG_158 (GP_HOST_TIMER) =  0

STREAM:  0  Register Read:

REG_0180 (MAIN_STREAM_HTOTAL) =  0
REG_0184 (MAIN_STREAM_VTOTAL) =  0
REG_0188 (MAIN_STREAM_POLARITY) =  0
REG_018C (MAIN_STREAM_HSWIDTH) =  0
REG_0190 (MAIN_STREAM_VSWIDTH) =  0
REG_0194 (MAIN_STREAM_HRES) =  0
REG_0198 (MAIN_STREAM_VRES) =  0
REG_019C (MAIN_STREAM_HSTART) =  2883584
REG_01A0 (MAIN_STREAM_VSTART) =  0
REG_01A4 (MAIN_STREAM_MISC0) =  0
REG_01A8 (MAIN_STREAM_MISC1) =  0
REG_01AC (MVID) =  0
REG_01B0 (TRANSFER_UNIT_CONFIG_SRC_0) =  11328
REG_01B4 (NVID) =  0
REG_01B8 (USER_PIXEL_COUNT) =  1
REG_01BC (USER_DATA_COUNT) =  0
REG_01C0 (MAIN_STREAM_INTERLACED) =  0
REG_01C4 (USER_SYNC_POLARITY) =  15
REG_01C8 (USER_CONTROL) =  0
REG_01CC (USER_CONTROL) =  2883584
REG_0500 (MST_ENABLE) =  0
REG_0504 (MST_PID_TABLE_INDEX) =  0
REG_0508 (MST_PID_TABLE_ENTRY) =  0
REG_050C (SST_SOURCE_SELECT) =  0
REG_0510 (MST_ALLOCATION_TRIGGER) =  0
REG_0514 (MST_PID_TABLE_SELECT) =  0
REG_0518 (MST_ACTIVE_PAYLOAD_TABLE) =  0
REG_0520 (MST_ACTIVE) =  0
REG_0524 (MST_LINK_FRAME_COUNT) =  0
REG_0528 (MSO_CONFIGURATION) =  0
REG_0528 (MSO_CONFIGURATION) =  0

STREAM:  0  Register Read:

REG_0180 (MAIN_STREAM_HTOTAL) =  0
REG_0184 (MAIN_STREAM_VTOTAL) =  0
REG_0188 (MAIN_STREAM_POLARITY) =  0
REG_018C (MAIN_STREAM_HSWIDTH) =  0
REG_0190 (MAIN_STREAM_VSWIDTH) =  0
REG_0194 (MAIN_STREAM_HRES) =  0
REG_0198 (MAIN_STREAM_VRES) =  0
REG_019C (MAIN_STREAM_HSTART) =  0
REG_01A0 (MAIN_STREAM_VSTART) =  0
REG_01A4 (MAIN_STREAM_MISC0) =  0
REG_01A8 (MAIN_STREAM_MISC1) =  0
REG_01AC (MVID) =  0
REG_01B0 (TRANSFER_UNIT_CONFIG_SRC_0) =  64
REG_01B4 (NVID) =  0
REG_01B8 (USER_PIXEL_COUNT) =  1
REG_01BC (USER_DATA_COUNT) =  0
REG_01C0 (MAIN_STREAM_INTERLACED) =  0
REG_01C4 (USER_SYNC_POLARITY) =  15
REG_01C8 (USER_CONTROL) =  0
REG_0500 (MST_ENABLE) =  0
REG_0504 (MST_PID_TABLE_INDEX) =  0
REG_0508 (MST_PID_TABLE_ENTRY) =  738197504
REG_050C (SST_SOURCE_SELECT) =  0
REG_0510 (MST_ALLOCATION_TRIGGER) =  0
REG_0514 (MST_PID_TABLE_SELECT) =  0
REG_0518 (MST_ACTIVE_PAYLOAD_TABLE) =  0
REG_0520 (MST_ACTIVE) =  0
REG_0524 (MST_LINK_FRAME_COUNT) =  0
REG_0528 (MSO_CONFIGURATION) =  0
REG_0528 (MSO_CONFIGURATION) =  0
-------------------------
Ux983_APB_dump
0x0 0x1
0x4 0x64
0x8 0x0
0xc 0x0
0x10 0x0
0x14 0x0
0x18 0x4
0x1c 0x14
0x20 0xc00
0x24 0x0
0x28 0x2f
0x2c 0x0
0x30 0x0
0x34 0x0
0x38 0xc
0x3c 0x0
0x40 0x0
0x44 0xc
0x48 0x0
0x4c 0x0
0x50 0x0
0x54 0x0
0x58 0x0
0x5c 0x0
0x60 0x0
0x64 0x0
0x68 0x0
0x6c 0x0
0x70 0x4
0x74 0xa
0x78 0x0
0x7c 0xc0000
0x80 0x1
0x84 0x0
0x88 0x0
0x8c 0x0
0x90 0x0
0x94 0x0
0x98 0x0
0x9c 0x0
0xa0 0x0
0xa4 0x0
0xa8 0x5
0xac 0x0
0xb0 0x0
0xb4 0x0
0xb8 0x0
0xbc 0x0
0xc0 0x0
0xc4 0x0
0xc8 0x0
0xcc 0x0
0xd0 0x0
0xd4 0x0
0xd8 0x1f02
0xdc 0xc0000
0xe0 0x0
0xe4 0x0
0xe8 0x0
0xec 0x2
0xf0 0x0
0xf4 0x0
0xf8 0x123404
0xfc 0xb0507
0x100 0xc
0x104 0x0
0x108 0x0
0x10c 0x0
0x110 0x0
0x114 0xc
0x118 0xc0000
0x11c 0x0
0x120 0x0
0x124 0x0
0x128 0x0
0x12c 0x0
0x130 0x0
0x134 0x0
0x138 0x0
0x13c 0x0
0x140 0x0
0x144 0x0
0x148 0x0
0x14c 0x0
0x150 0x0
0x154 0x0
0x158 0x0
0x15c 0xc00
0x160 0x0
0x164 0x0
0x168 0x0
0x16c 0xc
0x170 0x0
0x174 0xc000000
0x178 0x0
0x17c 0x0
0x180 0xfffffffeL
0x184 0x810
0x188 0x0
0x18c 0x310183
0x190 0x59
0x194 0x0
0x198 0xc0079
0x19c 0xc0000
0x1a0 0x7f
0x1a4 0xc0000
0x1a8 0x7f
0x1ac 0x0
0x1b0 0x0
0x1b4 0x0
0x1b8 0x0
0x1bc 0x0
0x1c0 0x0
0x1c4 0xc00
0x1c8 0x0
0x1cc 0x0
0x1d0 0x0
0x1d4 0x0
0x1d8 0x0
0x1dc 0x0
0x1e0 0x0
0x1e4 0x0
0x1e8 0x0
0x1ec 0x0
0x1f0 0x0
0x1f4 0x0
0x1f8 0x0
0x1fc 0x0
0x200 0x0
0x204 0x0
0x208 0xc
0x20c 0x0
0x210 0x0
0x214 0x2
0x218 0x0
0x21c 0x0
0x220 0x0
0x224 0x0
0x400 0x1e
0x404 0x4
0x408 0x1
0x40c 0x0
0x410 0x0
0x414 0x0
0x418 0x0
0x41c 0x0
0x420 0x0
0x424 0x0
0x428 0x0
0x42c 0x0
0x430 0x0
0x434 0x1
0x438 0x1
0x43c 0x30044
0x440 0x30044
0x444 0x0
0x448 0x0
0x44c 0x0
0x450 0x0
0x454 0x2020202
0x458 0x0
0x45c 0x0
0x460 0x0
0x464 0x0
0x468 0x0
0x46c 0x0
0x470 0x0
0x474 0x0
0x478 0x0
0x47c 0x0
0x480 0x0
0x484 0x3f3f3f3f
0x488 0x0
0x48c 0x0
0x490 0x80000000L
0x494 0x80000000L
0x498 0x80000000L
0x49c 0x80000000L
0x4a0 0x0
0x4a4 0x0
0x4a8 0x0
0x4ac 0x0
0x4b0 0x0
0x4b4 0x0
0x4b8 0x0
0x4bc 0x0
0x4c0 0x0
0x4c4 0x0
0x4c8 0x0
0x4cc 0x0
0x4d0 0x0
0x4d4 0x0
0x4d8 0x0
0x4dc 0x0
0x4e0 0x0
0x4e4 0x0
0x4e8 0x0
0x4ec 0x0
0x4f0 0x0
0x4f4 0x0
0x4f8 0x0
0x4fc 0x0
0x500 0x0
0x504 0x0
0x508 0x0
0x50c 0xc0000
0x510 0x0
0x514 0x0
0x518 0x0
0x51c 0x0
0x520 0x0
0x524 0x0
0x528 0x0
0x52c 0x0
0x530 0x0
0x534 0x0
0x538 0x19
0x53c 0xc00
0x700 0x0
0x704 0x0
0x708 0x0
0x70c 0x0
0x710 0x0
0x714 0x0
0x718 0x0
0x71c 0x0
0x720 0x0
0x800 0x0
0x804 0x0
0x808 0x0
0x80c 0x0
0x810 0x0
0x814 0x270
0x818 0x0
0x81c 0x2
0x820 0x90
0x824 0x270
0x828 0x0
0x82c 0x0
0x830 0x0
0x834 0x0
0x838 0x0
0x83c 0x0
0x840 0x0
0x844 0x0
0x848 0x0
0x84c 0x0
0x850 0x0
0x854 0x0
0x858 0x0
0x85c 0x0
0x860 0x0
0x864 0x0
0x868 0x0
0x86c 0x0
0x870 0x0
0x874 0x0
0x878 0x0
0x87c 0x0
0x880 0x0
0x884 0x0
0x888 0x0
0x88c 0xc00
0x890 0x0
0x894 0x0
0x898 0x0
0x89c 0x0
0x8a0 0x0
0x8a4 0x0
0x8a8 0x0
0x8ac 0x0
0x8b0 0x0
0x8b4 0x0
0x8b8 0x0
0x8bc 0x0
0x8c0 0x0
0x8c4 0x0
0x8c8 0x0
0x8cc 0x0
0x8d0 0x0
0x8d4 0x0
0x8d8 0x0
0x8dc 0x0
0x8e0 0x0
0x8e4 0x0
0x8e8 0x0
0x8ec 0x0
0x8f0 0x0
0x8f4 0x0
0x8f8 0x0
0x8fc 0x0
0x900 0x0
0x904 0x0
0x908 0x0
0x90c 0x0
0x910 0x0
0x914 0x0
0x918 0x0
0x91c 0x0
0x920 0xc000000
0x924 0x0
0x928 0x0
0x92c 0x0
0x930 0x0
0x934 0x0
0xa00 0x1
0xa04 0x4
0xa08 0x0
0xa0c 0x0
0xa10 0x0
0xa14 0x1
0xa18 0x5
0xa1c 0x8
0xa20 0xf
0xa24 0x1ff003f
0xa28 0x20
0xa2c 0xc0000
0xa30 0x78
0xa34 0x0
0xa38 0x0
0xa3c 0x0
0xa40 0x0
0xa44 0x0
0xa48 0x0
0xa4c 0x0
0xa50 0x0
0xa54 0x0
0xa58 0x0
0xa5c 0x0
0xa60 0x0
0xa64 0x0
0xa68 0x0
0xa6c 0x0
0xa70 0x0
0xa74 0x0
0xa78 0x0
0xa7c 0x0
0xa80 0x1
0xa84 0x0
0xa88 0x0
0xa8c 0x18
0xa90 0x4
0xa94 0x0
0xa98 0x0
0xa9c 0x76543210
0xaa0 0x0
0xaa4 0x0
0xaa8 0x0
0xaac 0x0
0xab0 0x0
0xab4 0x1
0xab8 0x0
0xabc 0x0
0xac0 0x0
0xac4 0x0
0xac8 0x0
0xacc 0x0
0xad0 0x0
0xad4 0x0
0xad8 0x0
0xadc 0x0
0xae0 0x0
0xae4 0x0
0xae8 0x2
0xaec 0x0
0xaf0 0x0
0xaf4 0x0
0xaf8 0x0
0xafc 0x0
0xb00 0x0
0xb04 0x4
0xb08 0x0
0xb0c 0x0
0xb10 0x0
0xb14 0x0
0xb18 0x0
0xb1c 0x8
0xb20 0xf
0xb24 0x1ff003f
0xb28 0xf000f
0xb2c 0x0
0xb30 0x78
0xb34 0xc0000
0xb38 0x0
0xb3c 0x0
0xb40 0x0
0xb44 0x0
0xb48 0x0
0xb4c 0x0
0xb50 0x0
0xb54 0x0
0xb58 0x0
0xb5c 0x0
0xb60 0x0
0xb64 0x0
0xb68 0x0
0xb6c 0x0
0xb70 0x0
0xb74 0x0
0xb78 0x0
0xb7c 0x0
0xb80 0x0
0xb84 0xc000001
0xb88 0x0
0xb8c 0x0
0xb90 0x0
0xb94 0x0
0xb98 0x0
0xb9c 0xc0000
0xba0 0x0
0xba4 0x0
0xba8 0x0
0xbac 0x0
0xbb0 0x0
0xbb4 0x0
0xbb8 0x0
0xbbc 0x0
0xbc0 0xc00
0xbc4 0x0
0xbc8 0x0
0xbcc 0x0
0xbd0 0x0
0xbd4 0x0
0xbd8 0xc00
0xbdc 0x0
0xbe0 0x0

这是我们的配置

"""
Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
ALL RIGHTS RESERVED
"""

"""
Global Setups - Do Not Change
"""

FPD4 = [0,0]
FPD4Rate = [0,0] 
FPD3Stream = [0,0] 
THW = [0,0,0,0]
TVW = [0,0,0,0]
AHW = [0,0,0,0] 
AVW = [0,0,0,0]
HBP = [0,0,0,0] 
VBP = [0,0,0,0] 
HSW = [0,0,0,0] 
VSW = [0,0,0,0] 
HFP = [0,0,0,0] 
VFP = [0,0,0,0] 
HSP = [0,0,0,0]
VSP = [0,0,0,0] 
PCLK = [0,0,0,0] 
Bits_per_pixel = [0,0,0,0] 
PATGEN = [0,0,0,0]
CropEnable = [0,0,0,0]
FilterEnable = [0,0,0,0]
CropXStart = [0,0,0,0]
CropXStop = [0,0,0,0]
CropYStart = [0,0,0,0]
CropYStop = [0,0,0,0]
FilterEnable = [0,0,0,0]
FilterA = [0,0,0,0]
FilterN = [0,0,0,0]
DSI_PORT0 = 0
DSI_PORT1 = 0
MAPSEL = [0,0]
OLDIBpp = [0,0]
HDCP_FPD3 = [0,0]
Des0_DaisyVPs = [0,0,0,0]
FPD4RateDaisy0 = [0,0,0]
FPD4RateDaisy1 = [0,0,0]
FPD4Daisy0 = [1,1]
DP0_ON = [0,0,0,0]
DP1_ON = [0,0,0,0]
DP_Output_0_Source = [0,0,0,0]
DP_Output_1_Source = [0,0,0,0]
Des_Device = [0,0,0,0]
DP_Rate = [0,0,0,0]
DP_Lane_Num = [0,0,0,0]
RGBMode = [0,0,0,0]
OLDIEnabled = [0,0,0,0]
MAPSEL0 = [0,0,0,0]
MAPSEL1 = [0,0,0,0]
RGBBpp = [0,0,0,0]
OLDIBpp0 = [0,0,0,0]
OLDIBpp1 = [0,0,0,0]
OLDI_RGB_Port0_Source = [0,0,0,0]
OLDI_Port1_Source = [0,0,0,0]
DaisyConf = [0,0,0,0]
FPD4LinkEN0 = [0,0,0,0]
FPD4LinkEN1 = [0,0,0,0]
DES_Display_SSCG = [0,0,0,0]
DES_Display_SSCG_FDEV = [0,0,0,0]
DES_Display_SSCG_FMOD = [0,0,0,0]
serFPDSSCG = [0,0]
serFPDSSCG_fdev = [0,0]
serFPDSSCG_fmod = [0,0]
eFuseOV = 0
FPD3DaisyVP_P0 = [0,0,0]
FPD3DaisyVP_P1 = [0,0,0]
DES_BC_SSCG = [0,0,0,0]
DES_BC_SSCG_FDEV = [0,0,0,0]
DES_BC_SSCG_FMOD = [0,0,0,0]
DP_Stream_BPP = [0,0]
MST_Source = [0,0,0,0]
DES_FC_SSCG = [0,0,0]
DES_FC_SSCG_FDEV = [0,0,0]
DES_FC_SSCG_FMOD = [0,0,0]
disable_FIFO_errata = 0
Override_Color = 0

""" 
General Configurations - Set by the user
"""
# Serializer Address 
# Ignore if using DES only configurations 
SER_Address = 0x18

# First deserializer Address Port 0
# For dual FPD-Link configurations use this address for the first deserializer. P1 addresses are ignored 
# For single port 0 or independent FPD configurations this is the address of the first DES attached to port 0
DES0_Address = 0x58
DES0_Alias = 0x58

# First deserializer Address Port 1
# Only used for single port 1 or independent FPD link configurations
P1DES0_Address = 0x58
P1DES0_Alias = 0x5c

# Deserializer Daisy Chain Addresses
DES1_Address = 0x58
DES1_Alias = 0x5e

DES2_Address = 0x58
DES2_Alias = 0x60

DES3_Address = 0x58
DES3_Alias = 0x62

# Serializer Device
# For FPD IV serializer, options are 983 or 981, HH983_ES1.0, HH983_CS1.0
# For FPD III serializer, options are 925, 926, 921, 929, 949, 941AS, 947
Device = "983"

# DES eFuse Override Enable
# Enabling eFuse override will generate a script to 
# manually override the eFuse settings for the DES 
# to the final production version when using either 984 or 988
eFuseOV = 0

# If Des_Only = 1, 98x Serialzier configuration will be ignored but 
# 94x/92x SER configuration will be included if Fes_FPD3_Only = 1
# Only applicable for configurations with 988/984 DES 
# Use this setting when the SER is 94x or 92x FPD III or to generate a 98x to 98x script 
# which only includes the DES side configurations
Des_Only = 0

# Select deserializer PatGen enable
# Only applicable for FPD IV DES configurations - ignore for FPD III DES configurations
# 0 = disable
# 1 = enable
DES_Patgen_on = 0

# Ignored for FPD IV configurations
# Set to 1 when using FPD IV serializer to FPD IV deserializer in FPD III link mode
# Set to 0 when using FPD III serializer to FPD IV deserializer 
FPD4DES_FPD3MODE = 0

# Set the deserializer FPD port configuration
# Ignored if serializer is 98x 
# Options: 
# FPD3 Dual = 5
# FPD3 Single Port 0 = 6
DES_FPDIII_Conf = 5

# Set the serializer FPD port configuration
# Options: 
# FPD4 Dual = 1
# FPD4 Single Port 0 = 2
# FPD4 Single Port 1 = 3
# FPD4 Independent = 4 
# FPD3 Dual = 5
# FPD3 Single Port 0 = 6
# FPD3 Single Port 1 = 7
# FPD3 Independent = 8 
# FPD4 Port 0/FPD3 Port 1 = 9 
# FPD3 Port 0/FPD4 Port 1 = 10 
FPDConf = 2

# Configure Y split daisy chain topology 
# In Y split daisy chain mode, the SER connects to two DES
# One or both of the connected DES connect to another downstream DES via daisy chain
# In Y split daisy chain mode deserializers are numbered as follows:
# SER Port 0 -> DES0 -> DES2
# SER Port 1 -> DES1 -> DES3
# Options: 
# 0: Straight line daisy chain mode: SER -> DES -> DES -> DES -> DES
# 1: Y Split daisy chain mode
y_split_daisy = 0

# Enable HDCP1.4 per FPD Channel in FPD III mode (Only applicable for UH to UH connections)
# Only used for FPD III mode
# Options: 0 = No HDCP, 1 = HDCP Enabled 
# HDCP[0] controls FPD port 0 
# HDCP[1] controls FPD port 1
# Unused FPD ports are ignored and only the HDCP[0] setting is used for dual FPD modes
HDCP_FPD3[0] = 0
HDCP_FPD3[1] = 0

# Enter number of VPs used
# Options:
# 1 Display = 1 (VP0)
# 2 Displays = 2 (VP0/VP1)
# 3 Displays = 3(VP0/VP1/VP2)
# 4 Displays = 4 (VP0/VP1/VP2/VP3)
numVPs = 1

# Enter Video Processor 0 Properties
# THW = Horizontal Total Pixels = AHW + HBP + HFP + HSW
# TVW = Vertical Total Lines = AVW + VBP + VFP + VSW
# AHW = Hoizontal Active Pixels
# AVW = Vertical Active Lines
# HBP = Horizontal Back Porch Pixels
# VBP = Vertical Back Porch Pixels
# HSW = Horizontal Sync Width Pixels
# VSW = Vertical Sync Width Lines
# HSP = Horizontal Sync Polarity: 0 = Positive, 1 = Negative
# VSP = Vertical Sync Polarity: 0 = Positive, 1 = Negative
# PCLK = Pixel Clock Rate in MHz 
# Bits_per_pixel = 18, 24, or 30 (30bpp only available for FPD IV)
# PATGEN = 1 - Generate PATGEN from the VP
# PATGEN = 0 - Configure the VP but don't enable PATGEN (use for end to end video)
# If Des is set to FPD3 mode only, VP0 timing is used to configure Des.
THW[0] = 2768
TVW[0] = 1652
AHW[0] = 2560
AVW[0] = 1600
HBP[0] = 60
VBP[0] = 18
HSW[0] = 60
VSW[0] = 2
HFP[0] = THW[0] - AHW[0] - HBP[0] - HSW[0]
VFP[0] = TVW[0] - AVW[0] - VBP[0] - VSW[0]
HSP[0] = 0
VSP[0] = 0
PCLK[0] = 274.3
Bits_per_pixel[0] = 24
PATGEN[0] = 1

# Crop and filter parameters (Optional - Ignored if CropEnable[x] is 0)
CropEnable[0] = 0
CropXStart[0] = 0
CropXStop[0] = 1399
CropYStart[0] = 0
CropYStop[0] = 1199
# Filter parameters (Optional - Ignored if FilterEnable[x] is 0)
FilterEnable[0] = 0
FilterA[0] = 1
FilterN[0] = 2

# Enter Video Processor 1 Properties (Optional)
THW[1] = 1650
TVW[1] = 750
AHW[1] = 1280
AVW[1] = 720
HBP[1] = 220
VBP[1] = 20
HSW[1] = 40
VSW[1] = 5
HFP[1] = THW[1] - AHW[1] - HBP[1] - HSW[1]
VFP[1] = TVW[1] - AVW[1] - VBP[1] - VSW[1]
HSP[1] = 0
VSP[1] = 0
PCLK[1] = 74.25
Bits_per_pixel[1] = 24
PATGEN[1] = 1

# Crop and filter parameters (Optional - Ignored if CropEnable[x] is 0)
CropEnable[1] = 0
CropXStart[1] = 1400
CropXStop[1] = 2799
CropYStart[1] = 0
CropYStop[1] = 1199
# Filter parameters (Optional - Ignored if FilterEnable[x] is 0)
FilterEnable[1] = 0
FilterA[1] = 1
FilterN[1] = 2

# Enter Video Processor 2 Properties (Optional)
THW[2] = 2020
TVW[2] = 590
AHW[2] = 1920
AVW[2] = 384
HBP[2] = 8
VBP[2] = 5
HSW[2] = 12
VSW[2] = 3
HFP[2] = THW[2] - AHW[2] - HBP[2] - HSW[2]
VFP[2] = TVW[2] - AVW[2] - VBP[2] - VSW[2]
HSP[2] = 0
VSP[2] = 0
PCLK[2] = 71.51
Bits_per_pixel[2] = 24
PATGEN[2] = 1

# Crop and filter parameters (Optional - Ignored if CropEnable[x] is 0)
CropEnable[2] = 1
CropXStart[2] = 2304
CropXStop[2] = 4223
CropYStart[2] = 0
CropYStop[2] = 383
# Filter parameters (Optional - Ignored if FilterEnable[x] is 0)
FilterEnable[2] = 0
FilterA[2] = 1
FilterN[2] = 2

# Enter Video Processor 3 Properties (Optional)
THW[3] = 2640
TVW[3] = 1500
AHW[3] = 2560
AVW[3] = 1440
HBP[3] = 40
VBP[3] = 40
HSW[3] = 32
VSW[3] = 10
HFP[3] = THW[3] - AHW[3] - HBP[3] - HSW[3]
VFP[3] = TVW[3] - AVW[3] - VBP[3] - VSW[3]
HSP[3] = 0
VSP[3] = 0
PCLK[3] = 100
Bits_per_pixel[3] = 24
PATGEN[3] = 0

# Crop and filter parameters (Optional - Ignored if CropEnable[x] is 0)
CropEnable[3] = 0
CropXStart[3] = 2560
CropXStop[3] = 3839
CropYStart[3] = 0
CropYStop[3] = 719
# Filter parameters (Optional - Ignored if FilterEnable[x] is 0)
FilterEnable[3] = 1
FilterA[3] = 1
FilterN[3] = 2

# Enter stream mapping for FPD3 Mode (ignored if using FPD4) 
# Ignore map setting for unused port in single FPD3 mode
# If using dual mode, set FPD3Stream[0] and FPD3Stream[1] to the same VP
# Options: 0 = VP0, 1 = VP1, 2 = VP2, 3 = VP3: Maps the corresponding VP to the FPD3 port 
FPD3Stream[0] = 0
FPD3Stream[1] = 0

# FPD4 Rate Selection (Gbps)
# Ignored if the port is set to FPD3 mode
# FPD4Rate[0] sets FPD TX Port 0
# FPD4Rate[1] sets FPD TX Port 1
# Options: 3.375, 6.75, 10.8, 13.5, 12.528
FPD4Rate[0] = 13.5
FPD4Rate[1] = 13.5

# FPD4 Port SSCG Configuration
# serFPDSSCG[0] controls FPD Port 0
# serFPDSSCG[1] controls FPD Port 1
# Options:
# 0 = Disabled
# 1 = Enable SSCG Center Spread
# 2 = Enable SSCG Down Spread
serFPDSSCG[0] = 0
serFPDSSCG[1] = 0

# Serializer SSCG FDEV %
# serFPDSSCG_fdev[0] controls FPD Port 0
# serFPDSSCG_fdev[1] controls FPD Port 1
# Ignored is serFPDSSCG = 0
# Sets the SSCG frequency deviation percentage for FPD4 port 0
# Options: 0-0.5 (%)
serFPDSSCG_fdev[0] = 0.5
serFPDSSCG_fdev[1] = 0.5

# Display SSCG FMOD kHz 
# serFPDSSCG_fmod[0] controls FPD Port 0
# serFPDSSCG_fmod[1] controls FPD Port 1
# Ignored is DES_Display_SSCG = 0
# Set the SSCG modulation frequency for display interface SSCG 
# Options: 30-33 (kHz) 
serFPDSSCG_fmod[0] = 33
serFPDSSCG_fmod[1] = 33

# FPD4 Link Layer Selection for independent FPD IV Mode or mixed FPD III/IV modes
# Ignored for dual FPD IV or single FPD IV modes
# Select which VPs are forwarded to FPD Port 0 and Port 1 Link layers
# FPD4LinkEN0 controls SER FPD Port 0
# FPD4LinkEN1 controls SER FPD Port 1
# For example, to send VP 0 to port 0 and VP1 to port 1, use the following
# Note that in order to send any stream to both FPD ports, the FPD IV links rate must be the same 
# FPD4LinkEN0 = [1,0,0,0]
# FPD4LinkEN1 = [0,1,0,0]
FPD4LinkEN0 = [1,0,0,0]
FPD4LinkEN1 = [0,1,0,0]

"""
983 Configs - Ignored if using 981
"""
# Disable DP FIFO Errata for debug 
# Set to 1 in order to disable DP FIFO errata. The FIFO errata will restrict 983 operation to only the
# configured lane rate/lane count settings below. If the DP source lane count/rate are unknown or variable, 
# disable the FIFO errata to test. TI recommends to apply the errata for optimal performance on production systems
disable_FIFO_errata = 1

# Set max DP lane count
# Options: 1, 2, 4
# Note - for UH983 or UB983, this setting must be set to the desired lane count for DP FIFO errata to execute sucessfully 
DPlanes = 4

# Set max advertised DP lane rate in Gbps
# Options: 1.62, 2.7, 5.4, 8.1
# Note - for UH983 or UB983, this setting must be set to the desired link rate for DP FIFO errata to execute sucessfully 
maxRate = 2.7

# Set MST or SST mode
# Options: 0 = SST mode, 1 = MST mode
# MST mode always uses VP0 for MST0 and VP1 for MST1
MST = 0

# Set which MST stream is mapped to each video processor 
# Only used when MST = 1
# Options:
# 0: Video processor is mapped to MST0
# 1: Video processor is mapped to MST1
# Assignments: [VP0,VP1,VP2,VP3]
MST_Source = [0,1,0,0]

# Set DP receiver to expect SSC or no SSC from the DPTX
# This setting also configures the MAX_DOWNSPREAD capability bit in DPCD 0x00003[0]
# Options: 0 = No SSC, 1 = SSC
SSC = 0

#Set DP receiver to DP or eDP mode 
# Options: 0 = DP Mode, 1 = eDP Mode
eDP = 0

# Set DP Stream BPP (Mandatory for HH983 ES1.0 and CS1.0, Optional for Ux983)
# Options: 30, 24, 18
# For SST, only stream 0 is used [stream0,0]
# For MST, format is [stream0,stream1]
# Example: Stream 0 is 24 bpp, Stream 1 is 30bpp
# Example Setting: [24,30]
DP_Stream_BPP = [24,24]

# Optional setting for Ux983 to override colorimetry for incoming streams 
# When enabled, the SER will ignore colorimetry information from MSA 
# and use the DP_Stream_BPP setting instead. This setting can improve error tolerance 
# in high noise environments. CAUTION: The DP_Stream_BPP setting must match the colorimetry 
# from the incoming video source, otherwise video distrotion or video wrap around will occur
Override_Color = 0

# EDID Options (SST only)
# Options: 
# 0: EDID Support Disabled
# 1: EDID location = Internal SRAM using I2C1 bus
# 2: EDID location = Internal SRAM using I2C2 bus
# 3: EDID location = External EEPROM on HH983 I2C0 bus
# 4: EDID location = External EEPROM on HH983 I2C1 bus
# 5: EDID location = External EEPROM on HH983 I2C2 bus
# Note that the Internal SRAM EDID Example EDID included with the generated config for option 1
# does not change based on the VP settings. Custom EDIDs can be generated with external
# off the shelf free tools to replace the example EDID if needed
EDID = 0

# EDID 8-bit I2C Address (HH983 only)
EDID_ADDR = 0xA0

"""
981 Configs - Ignored if using 983
"""
#DSI ports active
# 0 = DSI 0 only
# 1 = DSI 1 only
# 2 = DSI 0 and DSI 1
DSI_PORTS_ACTIVE = 0

# Set max DSI lane count
# Options: 1, 2, 3, 4
Port0_DSI_Lanes = 4
Port1_DSI_Lanes = 4

# Set DSI in Continuous or Non-Continuous Clock
# 1 = Continuous ; 0 = Non-Continuous Clock
Port0_Contin = 1
Port1_Contin = 1

# Set the DSI rate
# example: 500 Mbps= 500, 1.2 Gbps = 1200Mbps
Port0_DSI_Rate = 891
Port1_DSI_Rate = 891

#DSI Source for Video Processors
#0 = DPHY 0 virtual Channel 0
#1 = DPHY 0 virtual Channel 1
#2 = DPHY 0 virtual Channel 2
#3 = DPHY 0 virtual Channel 3
#4 = DPHY 1 virtual Channel 0
#5 = DPHY 1 virtual Channel 1
#6 = DPHY 1 virtual Channel 2
#7 = DPHY 1 virtual Channel 3
VP_0_Source = 0
VP_1_Source = 0
VP_2_Source = 0
VP_3_Source = 0

"""
#####################################
DES0 (First Deserialzier) Configurations - Ignored for FPD III Modes
This section is referenced for FPD IV Dual mode or Single FPD IV Port 0 mode (NOT FPD IV Single Port 1 Mode)
#####################################
"""
# Des_Device 
# Only used for FPD IV deserializer configurations - ignore if using FPD III deserializer
# Options 984, 988, HH984_CS1.0
Des_Device[0] = "984" 

# Set the deserializer Daisy Chain TX FPD port configuration
# Options: 
# Daisy Chaining Disabled = 0
# FPD4 Dual = 1
# FPD4 Single Port 0 = 2
# FPD4 Single Port 1 = 3 # Net yet functional
# FPD4 Independent = 4 # Net yet functional
# FPD3 Dual = 5
# FPD3 Single Port 0 = 6
# FPD3 Single Port 1 = 7
# FPD3 Independent = 8 
# FPD4 Port 0/FPD3 Port 1 = 9 # Net yet functional
# FPD3 Port 0/FPD4 Port 1 = 10 # Net yet functional
DaisyConf[0] = 0

# Enable daisy chain TX forwarding for deserializer 0 (first DES in the chain)
# Set VPs 0-4 = 1 to enable forwarding of that VP to the next DES 
# If all VP forwarding is set to 0, then daisy chaining is disabled
# Example: Forward only VP0 to the next DES:    Des0_DaisyVPs = [1,0,0,0]
# Example Forward VP1 and VP2 to the next DES:  Des0_DaisyVPs = [0,1,1,0]
Des0_DaisyVPs = [0,1,0,0]

# Set which VP is forwarded to chain chain output in FPD III mode
# FPD3DaisyVP_P0 controls daisy chain FPD port 0
# FPD3DaisyVP_P1 controls daisy chain FPD port 1
# FPD3DaisyVP_P0 and FPD3DaisyVP_P1 must be set to the same VP for dual FPD III mode
# Setting the daisy chain output to FPD III mode terminates the daisy chain at the connected deserializer
# This is ignored if the daisy chain is set up for FPD IV output mode
# Example: Forward VP1 to Daisy Chain Output in FPD III mode: FPD3DaisyVP[0] = 1
# Example: Forward VP3 to Daisy Chain Output in FPD III mode: FPD3DaisyVP[0] = 3
FPD3DaisyVP_P0[0] = 1
FPD3DaisyVP_P1[0] = 1

# FPD4 Rate Selection for DES0 Daisy Chain TX (Gbps)
# Ignored if the port is set to FPD3 mode
# FPD4RateDaisy0[0] sets DES0 Daisy Chain TX Port 0
# FPD4RateDaisy1[0] sets DES0 Daisy Chain TX Port 1
# Options: 3.375, 6.75, 10.8, 13.5, 12.528
FPD4RateDaisy0[0] = 6.75
FPD4RateDaisy1[0] = 6.75

# DES Daisy Chain FC SSCG Configuration
# SSCG options for the deserializer forward channel output
# Options:
# 0 = Disable SSCG on FPD forward channel daisy chain interface 
# 1 = Enable SSCG with Center Spread
# 2 = Enable SSCg with Down Spread
DES_FC_SSCG[0] = 0

# FPD Daisy Chain FC SSCG FDEV %
# Ignored is DES_FC_SSCG = 0
# Sets the SSCG frequency deviation percentage for daisy chain forward channel interface SSCG 
# Note: Combined FPD FC and BC FDEV should not exceed 0.5% for center spread or 0.25% for down spread
# Options: 0-0.5 (%) in Center Spread Mode
# Options: 0-0.25 (%) in Down Spread Mode
DES_FC_SSCG_FDEV[0] = 0.25

# DES Daisy Chain SSCG FMOD kHz 
# Ignored is DES_FC_SSCG = 0
# Set the SSCG modulation frequency for daisy chain forward channel interface SSCG 
# Options: 30-33 (kHz) 
DES_FC_SSCG_FMOD[0] = 33

# FPD BC SSCG Configuration 
# SSCG options for the deserializer back channel output
# Options:
# 0 = Disable SSCG on FPD back channel interface 
# 1 = Enable SSCG with Center Spread 
# 2 = Enable SSCG with Down Spread 
DES_BC_SSCG[0] = 0

# FPD BC SSCG FDEV %
# Ignored is DES_BC_SSCG = 0
# Sets the SSCG frequency deviation percentage for FPD back channel interface SSCG 
# Note: Combined FPD FC and BC FDEV should not exceed 0.5% for center spread or 0.25% for down spread
# Options: 0-0.5 (%) in Center Spread Mode
# Options: 0-0.25 (%) in Down Spread Mode
DES_BC_SSCG_FDEV[0] = 0.25

# FPD SSCG FMOD kHz 
# Ignored is DES_BC_SSCG = 0
# Set the SSCG modulation frequency for FPD back channel interface SSCG 
# Options: 30-33 (kHz) 
DES_BC_SSCG_FMOD[0] = 33

# Display SSCG Configuration 
# SSCG options for the deserializer display output (OLDI or DP/eDP Interface)
# This is independent of the FPD-Link SSCG
# Options:
# 0 = Disable SSCG on display interface 
# 1 = Enable SSCG with Center Spread (988 only)
# 2 = Enable SSCG with Down Spread 
DES_Display_SSCG[0] = 0

# Display SSCG FDEV %
# Ignored is DES_Display_SSCG = 0
# Sets the SSCG frequency deviation percentage for display interface SSCG 
# Options: 0-6 (%) for 988 in Center Spread Mode (+/-3%)
# Options: 0-3 (%) for 988 in Down Spread Mode
# Options: 0-0.5 (%) for 984 (Down Spread Only)
DES_Display_SSCG_FDEV[0] = 0.5

# Display SSCG FMOD kHz 
# Ignored is DES_Display_SSCG = 0
# Set the SSCG modulation frequency for display interface SSCG 
# Options: 10-100 (kHz) for 988
# Options: 30-33 (kHz) for 984
DES_Display_SSCG_FMOD[0] = 33

"""
#####################################
DES0 (First Deserialzier) Configurations - Ignored for FPD III Modes
#####################################
"""

"""
DES0 984 Configs - Ignored if using 988
"""
#Select DP ports to be enabled
# Enabled = 1, Disabled = 0
DP0_ON[0] = 0
DP1_ON[0] = 1

#Select video source for DP output 
#Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. 
# 0 = Stream 0
# 1 = Stream 1
# 2 = Stream 2
# 3 = Stream 3
DP_Output_0_Source[0] = 1
DP_Output_1_Source[0] = 0

# Select DP output lane rate and number of lanes
# Options (in Gbps):
# 1.62
# 2.7
# 5.4
# 8.1
DP_Rate[0] = 2.7
DP_Lane_Num[0] = 4

"""
DES0 988 Configs - Ignored if using 984
"""
# Select OLDI or RGB mode 
# Options:
# 1 = RGB Mode Enabled
# 0 = OLDI Mode
RGBMode[0] = 0

# Select OLDI port configuration (Ignored for RGB mode)
# Options:
# 0 = Single OLDI port 0
# 1 = Single OLDI port 1
# 2 = Dual OLDI 
# 3 = Dual OLDI Swap
OLDIEnabled[0] = 1

# Select MAPSEL Setting for port 0 and port 1 (Ignored for RGB mode)
# 0 = MAPSEL = L (LSB on D3/D4)
# 1 = MAPSEL = H (MSB on D3/D4)
MAPSEL0[0] = 1
MAPSEL1[0] = 1

# Set OLDI Bits Per Pixel for port 0 and 1 (Ignored in RGB mode)
# Options: 18, 24, 30
OLDIBpp0[0] = 24
OLDIBpp1[0] = 24

# Set RGB mode Bits Per Pixel (Ignored in OLDI mode)
RGBBpp[0] = 24

# Select video source for OLDI/RGB output 
# Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. 
# For Dual OLDI, use same stream for both ports
# OLDI_Port1_Source is ignored for single OLDI port 0 or RGB mode
# OLDI_RGB_Port0_Source is ignored for single OLDI port 1 mode
# 0 = Stream 0
# 1 = Stream 1
# 2 = Stream 2
# 3 = Stream 3
OLDI_RGB_Port0_Source[0] = 0
OLDI_Port1_Source[0] = 0

"""
#####################################
DES1 (Second Deserialzier) Configurations - Ignored for FPD III Modes
For Y-split (Independent FPD IV) configurations, DES1 is the device attached to SER TX port 1
For single port 1 FPD IV configurations, this is the device attached to SER TX port 1
#####################################
"""
# Des_Device 
# Only used for FPD IV deserializer configurations - ignore if using FPD III deserializer
# Options 984, 988, HH984_CS1.0
Des_Device[1] = "988" 

# Set the deserializer Daisy Chain TX FPD port configuration
# Options: 
# Daisy Chaining Disabled = 0
# FPD4 Dual = 1
# FPD4 Single Port 0 = 2
# FPD4 Single Port 1 = 3 # Net yet functional
# FPD4 Independent = 4 # Net yet functional
# FPD3 Dual = 5
# FPD3 Single Port 0 = 6
# FPD3 Single Port 1 = 7
# FPD3 Independent = 8 
# FPD4 Port 0/FPD3 Port 1 = 9 # Net yet functional
# FPD3 Port 0/FPD4 Port 1 = 10 # Net yet functional
DaisyConf[1] = 0

# Enable daisy chain TX forwarding for deserializer 1 (second DES in the chain)
# Set VPs 0-4 = 1 to enable forwarding of that VP to the next DES 
# If all VP forwarding is set to 0, then daisy chaining is disabled
# Example: Forward only VP0 to the next DES:    Des1_DaisyVPs = [1,0,0,0]
# Example Forward VP1 and VP2 to the next DES:  Des1_DaisyVPs = [0,1,1,0]
Des1_DaisyVPs = [0,0,0,1]

# Set which VP is forwarded to chain chain output in FPD III mode
# FPD3DaisyVP_P0 controls daisy chain FPD port 0
# FPD3DaisyVP_P1 controls daisy chain FPD port 1
# FPD3DaisyVP_P0 and FPD3DaisyVP_P1 must be set to the same VP for dual FPD III mode
# Setting the daisy chain output to FPD III mode terminates the daisy chain at the connected deserializer
# This is ignored if the daisy chain is set up for FPD IV output mode
# Example: Forward VP1 to Daisy Chain Output in FPD III mode: FPD3DaisyVP[0] = 1
# Example: Forward VP3 to Daisy Chain Output in FPD III mode: FPD3DaisyVP[0] = 3
FPD3DaisyVP_P0[1] = 2
FPD3DaisyVP_P1[1] = 2

# FPD4 Rate Selection for DES1 Daisy Chain TX (Gbps)
# Ignored if the port is set to FPD3 mode
# FPD4RateDaisy0[1] sets DES1 Daisy Chain TX Port 0
# FPD4RateDaisy1[1] sets DES1 Daisy Chain TX Port 1
# Options: 3.375, 6.75, 10.8, 13.5, 12.528
FPD4RateDaisy0[1] = 3.375
FPD4RateDaisy1[1] = 3.375

# DES Daisy Chain FC SSCG Configuration
# SSCG options for the deserializer forward channel output
# Options:
# 0 = Disable SSCG on FPD forward channel daisy chain interface 
# 1 = Enable SSCG with Center Spread
# 2 = Enable SSCg with Down Spread
DES_FC_SSCG[1] = 0

# FPD Daisy Chain FC SSCG FDEV %
# Ignored is DES_FC_SSCG = 0
# Sets the SSCG frequency deviation percentage for daisy chain forward channel interface SSCG 
# Note: Combined FPD FC and BC FDEV should not exceed 0.5% for center spread or 0.25% for down spread
# Options: 0-0.5 (%) in Center Spread Mode
# Options: 0-0.25 (%) in Down Spread Mode
DES_FC_SSCG_FDEV[1] = 0.25

# DES Daisy Chain SSCG FMOD kHz 
# Ignored is DES_FC_SSCG = 0
# Set the SSCG modulation frequency for daisy chain forward channel interface SSCG 
# Options: 30-33 (kHz) 
DES_FC_SSCG_FMOD[1] = 33

# FPD BC SSCG Configuration 
# SSCG options for the deserializer back channel output
# Options:
# 0 = Disable SSCG on FPD back channel interface 
# 1 = Enable SSCG with Center Spread 
# 2 = Enable SSCG with Down Spread 
DES_BC_SSCG[1] = 0

# FPD BC SSCG FDEV %
# Ignored is DES_BC_SSCG = 0
# Sets the SSCG frequency deviation percentage for FPD back channel interface SSCG 
# Note: Combined FPD FC and BC FDEV should not exceed 0.5% for center spread or 0.25% for down spread
# Options: 0-0.5 (%) in Center Spread Mode
# Options: 0-0.25 (%) in Down Spread Mode
DES_BC_SSCG_FDEV[1] = 0.25

# FPD SSCG FMOD kHz 
# Ignored is DES_BC_SSCG = 0
# Set the SSCG modulation frequency for FPD back channel interface SSCG 
# Options: 30-33 (kHz) 
DES_BC_SSCG_FMOD[1] = 33

# Display SSCG Configuration 
# SSCG options for the deserializer display output (OLDI or DP/eDP Interface)
# This is independent of the FPD-Link SSCG
# Options:
# 0 = Disable SSCG on display interface 
# 1 = Enable SSCG with Center Spread 
# 2 = Enable SSCG with Down Spread 
DES_Display_SSCG[1] = 0

# Display SSCG FDEV %
# Ignored is DES_Display_SSCG = 0
# Sets the SSCG frequency deviation percentage for display interface SSCG 
# Options: 0-6 (%) for 988 in Center Spread Mode (+/-3%)
# Options: 0-3 (%) for 988 in Down Spread Mode
# Options: 0-0.5 (%) for 984 (Down Spread Only)
DES_Display_SSCG_FDEV[1] = 0.75

# Display SSCG FMOD kHz 
# Ignored is DES_Display_SSCG = 0
# Set the SSCG modulation frequency for display interface SSCG 
# Options: 10-100 (kHz) for 988
# Options: 30-33 (kHz) for 984
DES_Display_SSCG_FMOD[1] = 10

"""
#####################################
DES1 (Second Deserialzier) Configurations
#####################################
"""

"""
DES1 984 Configs - Ignored if using 988
"""
#Select DP ports to be enabled
# Enabled = 1, Disabled = 0
DP0_ON[1] = 1
DP1_ON[1] = 0

#Select video source for DP output 
#Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. 
# 0 = Stream 0
# 1 = Stream 1
# 2 = Stream 2
# 3 = Stream 3
DP_Output_0_Source[1] = 1
DP_Output_1_Source[1] = 0

# Select DP output lane rate and number of lanes
# Options (in Gbps):
# 1.62
# 2.7
# 5.4
# 8.1
DP_Rate[1] = 2.7
DP_Lane_Num[1] = 4

"""
DES1 988 Configs - Ignored if using 984
"""
# Select OLDI or RGB mode 
# Options:
# 1 = RGB Mode Enabled
# 0 = OLDI Mode
RGBMode[1] = 0

# Select OLDI port configuration (Ignored for RGB mode)
# Options:
# 0 = Single OLDI port 0
# 1 = Single OLDI port 1
# 2 = Dual OLDI 
# 3 = Dual OLDI Swap
OLDIEnabled[1] = 0

# Select MAPSEL Setting for port 0 and port 1 (Ignored for RGB mode)
# 0 = MAPSEL = L (LSB on D3/D4)
# 1 = MAPSEL = H (MSB on D3/D4)
MAPSEL0[1] = 1
MAPSEL1[1] = 1

# Set OLDI Bits Per Pixel for port 0 and 1 (Ignored in RGB mode)
# Options: 18, 24, 30
OLDIBpp0[1] = 24
OLDIBpp1[1] = 24

# Set RGB mode Bits Per Pixel (Ignored in OLDI mode)
RGBBpp[1] = 24

# Select video source for OLDI/RGB output 
# Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. 
# For Dual OLDI, use same stream for both ports
# OLDI_Port1_Source is ignored for single OLDI port 0 or RGB mode
# OLDI_RGB_Port0_Source is ignored for single OLDI port 1 mode
# 0 = Stream 0
# 1 = Stream 1
# 2 = Stream 2
# 3 = Stream 3
OLDI_RGB_Port0_Source[1] = 1
OLDI_Port1_Source[1] = 1

"""
#####################################
DES2 (Third Deserialzier) Configurations
#####################################
"""
# Des_Device 
# Only used for FPD IV deserializer configurations - ignore if using FPD III deserializer
# Options 984, 988, HH984_CS1.0
Des_Device[2] = "984" 

# Set the deserializer Daisy Chain TX FPD port configuration
# Options: 
# Daisy Chaining Disabled = 0
# FPD4 Dual = 1
# FPD4 Single Port 0 = 2
# FPD4 Single Port 1 = 3 # Net yet functional
# FPD4 Independent = 4 # Net yet functional
# FPD3 Dual = 5
# FPD3 Single Port 0 = 6
# FPD3 Single Port 1 = 7
# FPD3 Independent = 8 
# FPD4 Port 0/FPD3 Port 1 = 9 # Net yet functional
# FPD3 Port 0/FPD4 Port 1 = 10 # Net yet functional
DaisyConf[2] = 0

# Enable daisy chain TX forwarding for deserializer 2 (third DES in the chain)
# Set VPs 0-4 = 1 to enable forwarding of that VP to the next DES 
# If all VP forwarding is set to 0, then daisy chaining is disabled
# Example: Forward only VP0 to the next DES:    Des2_DaisyVPs = [1,0,0,0]
# Example Forward VP1 and VP2 to the next DES:  Des2_DaisyVPs = [0,1,1,0]
Des2_DaisyVPs = [0,0,0,1]

# Set which VP is forwarded to chain chain output in FPD III mode
# FPD3DaisyVP_P0 controls daisy chain FPD port 0
# FPD3DaisyVP_P1 controls daisy chain FPD port 1
# FPD3DaisyVP_P0 and FPD3DaisyVP_P1 must be set to the same VP for dual FPD III mode
# Setting the daisy chain output to FPD III mode terminates the daisy chain at the connected deserializer
# This is ignored if the daisy chain is set up for FPD IV output mode
# Example: Forward VP1 to Daisy Chain Output in FPD III mode: FPD3DaisyVP[0] = 1
# Example: Forward VP3 to Daisy Chain Output in FPD III mode: FPD3DaisyVP[0] = 3
FPD3DaisyVP_P0[2] = 1
FPD3DaisyVP_P1[2] = 1

# FPD4 Rate Selection for DES2 Daisy Chain TX (Gbps)
# Ignored if the port is set to FPD3 mode
# FPD4RateDaisy0[2] sets DES2 Daisy Chain TX Port 0
# FPD4RateDaisy1[2] sets DES2 Daisy Chain TX Port 1
# Options: 3.375, 6.75, 10.8, 13.5, 12.528
FPD4RateDaisy0[2] = 10.8
FPD4RateDaisy1[2] = 10.8

# DES Daisy Chain FC SSCG Configuration
# SSCG options for the deserializer forward channel output
# Options:
# 0 = Disable SSCG on FPD forward channel daisy chain interface 
# 1 = Enable SSCG with Center Spread
# 2 = Enable SSCg with Down Spread
DES_FC_SSCG[2] = 0

# FPD Daisy Chain FC SSCG FDEV %
# Ignored is DES_FC_SSCG = 0
# Sets the SSCG frequency deviation percentage for daisy chain forward channel interface SSCG 
# Note: Combined FPD FC and BC FDEV should not exceed 0.5% for center spread or 0.25% for down spread
# Options: 0-0.5 (%) in Center Spread Mode
# Options: 0-0.25 (%) in Down Spread Mode
DES_FC_SSCG_FDEV[2] = 0.25

# DES Daisy Chain SSCG FMOD kHz 
# Ignored is DES_FC_SSCG = 0
# Set the SSCG modulation frequency for daisy chain forward channel interface SSCG 
# Options: 30-33 (kHz) 
DES_FC_SSCG_FMOD[2] = 33

# FPD BC SSCG Configuration 
# SSCG options for the deserializer back channel output
# Options:
# 0 = Disable SSCG on FPD back channel interface 
# 1 = Enable SSCG with Center Spread 
# 2 = Enable SSCG with Down Spread 
DES_BC_SSCG[2] = 0

# FPD BC SSCG FDEV %
# Ignored is DES_BC_SSCG = 0
# Sets the SSCG frequency deviation percentage for FPD back channel interface SSCG 
# Note: Combined FPD FC and BC FDEV should not exceed 0.5% for center spread or 0.25% for down spread
# Options: 0-0.5 (%) in Center Spread Mode
# Options: 0-0.25 (%) in Down Spread Mode
DES_BC_SSCG_FDEV[2] = 0.25

# FPD SSCG FMOD kHz 
# Ignored is DES_BC_SSCG = 0
# Set the SSCG modulation frequency for FPD back channel interface SSCG 
# Options: 30-33 (kHz) 
DES_BC_SSCG_FMOD[2] = 33

# Display SSCG Configuration 
# SSCG options for the deserializer display output (OLDI or DP/eDP Interface)
# This is independent of the FPD-Link SSCG
# Options:
# 0 = Disable SSCG on display interface 
# 1 = Enable SSCG with Center Spread 
# 2 = Enable SSCG with Down Spread 
DES_Display_SSCG[2] = 0

# Display SSCG FDEV %
# Ignored is DES_Display_SSCG = 0
# Sets the SSCG frequency deviation percentage for display interface SSCG 
# Options: 0-6 (%) for 988 in Center Spread Mode (+/-3%)
# Options: 0-3 (%) for 988 in Down Spread Mode
# Options: 0-0.5 (%) for 984 (Down Spread Only)
DES_Display_SSCG_FDEV[2] = 1

# Display SSCG FMOD kHz 
# Ignored is DES_Display_SSCG = 0
# Set the SSCG modulation frequency for display interface SSCG 
# Options: 10-100 (kHz) for 988
# Options: 30-33 (kHz) for 984
DES_Display_SSCG_FMOD[2] = 50

"""
DES2 984 Configs - Ignored if using 988
"""
#Select DP ports to be enabled
# Enabled = 1, Disabled = 0
DP0_ON[2] = 1
DP1_ON[2] = 0

#Select video source for DP output 
#Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. 
# 0 = Stream 0
# 1 = Stream 1
# 2 = Stream 2
# 3 = Stream 3
DP_Output_0_Source[2] = 2
DP_Output_1_Source[2] = 2

# Select DP output lane rate and number of lanes
# Options (in Gbps):
# 1.62
# 2.7
# 5.4
# 8.1
DP_Rate[2] = 2.7
DP_Lane_Num[2] = 4

"""
DES2 988 Configs - Ignored if using 984
"""
# Select OLDI or RGB mode 
# Options:
# 1 = RGB Mode Enabled
# 0 = OLDI Mode
RGBMode[2] = 0

# Select OLDI port configuration (Ignored for RGB mode)
# Options:
# 0 = Single OLDI port 0
# 1 = Single OLDI port 1
# 2 = Dual OLDI 
# 3 = Dual OLDI Swap
OLDIEnabled[2] = 0

# Select MAPSEL Setting for port 0 and port 1 (Ignored for RGB mode)
# 0 = MAPSEL = L (LSB on D3/D4)
# 1 = MAPSEL = H (MSB on D3/D4)
MAPSEL0[2] = 1
MAPSEL1[2] = 1

# Set OLDI Bits Per Pixel for port 0 and 1 (Ignored in RGB mode)
# Options: 18, 24, 30
OLDIBpp0[2] = 18
OLDIBpp1[2] = 18

# Set RGB mode Bits Per Pixel (Ignored in OLDI mode)
RGBBpp[2] = 24

# Select video source for OLDI/RGB output 
# Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. 
# For Dual OLDI, use same stream for both ports
# OLDI_Port1_Source is ignored for single OLDI port 0 or RGB mode
# OLDI_RGB_Port0_Source is ignored for single OLDI port 1 mode
# 0 = Stream 0
# 1 = Stream 1
# 2 = Stream 2
# 3 = Stream 3
OLDI_RGB_Port0_Source[2] = 2
OLDI_Port1_Source[2] = 2

"""
#####################################
DES3 (Fourth Deserialzier) Configurations
#####################################
"""
# Des_Device 
# Only used for FPD IV deserializer configurations - ignore if using FPD III deserializer
# Options 984, 988, HH984_CS1.0
Des_Device[3] = "984" 

# FPD BC SSCG Configuration 
# SSCG options for the deserializer back channel output
# Options:
# 0 = Disable SSCG on FPD back channel interface 
# 1 = Enable SSCG with Center Spread 
# 2 = Enable SSCG with Down Spread 
DES_BC_SSCG[3] = 0

# FPD BC SSCG FDEV %
# Ignored is DES_BC_SSCG = 0
# Sets the SSCG frequency deviation percentage for FPD back channel interface SSCG 
# Note: Combined FPD FC and BC FDEV should not exceed 0.5% for center spread or 0.25% for down spread
# Options: 0-0.5 (%) in Center Spread Mode
# Options: 0-0.25 (%) in Down Spread Mode
DES_BC_SSCG_FDEV[3] = 0.25

# FPD SSCG FMOD kHz 
# Ignored is DES_BC_SSCG = 0
# Set the SSCG modulation frequency for FPD back channel interface SSCG 
# Options: 30-33 (kHz) 
DES_BC_SSCG_FMOD[3] = 33

# Display SSCG Configuration 
# SSCG options for the deserializer display output (OLDI or DP/eDP Interface)
# This is independent of the FPD-Link SSCG
# Options:
# 0 = Disable SSCG on display interface 
# 1 = Enable SSCG with Center Spread 
# 2 = Enable SSCG with Down Spread 
DES_Display_SSCG[3] = 0

# Display SSCG FDEV %
# Ignored is DES_Display_SSCG = 0
# Sets the SSCG frequency deviation percentage for display interface SSCG 
# Options: 0-6 (%) for 988 in Center Spread Mode (+/-3%)
# Options: 0-3 (%) for 988 in Down Spread Mode
# Options: 0-0.5 (%) for 984 (Down Spread Only)
DES_Display_SSCG_FDEV[3] = 0

# Display SSCG FMOD kHz 
# Ignored is DES_Display_SSCG = 0
# Set the SSCG modulation frequency for display interface SSCG 
# Options: 10-100 (kHz) for 988
# Options: 30-33 (kHz) for 984
DES_Display_SSCG_FMOD[3] = 50

"""
DES3 984 Configs - Ignored if using 988
"""
#Select DP ports to be enabled
# Enabled = 1, Disabled = 0
DP0_ON[3] = 1
DP1_ON[3] = 0

#Select video source for DP output 
#Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. 
# 0 = Stream 0
# 1 = Stream 1
# 2 = Stream 2
# 3 = Stream 3
DP_Output_0_Source[3] = 3
DP_Output_1_Source[3] = 3

# Select DP output lane rate and number of lanes
# Options (in Gbps):
# 1.62
# 2.7
# 5.4
# 8.1
DP_Rate[3] = 2.7
DP_Lane_Num[3] = 4

"""
DES3 988 Configs - Ignored if using 984
"""
# Select OLDI or RGB mode 
# Options:
# 1 = RGB Mode Enabled
# 0 = OLDI Mode
RGBMode[3] = 0

# Select OLDI port configuration (Ignored for RGB mode)
# Options:
# 0 = Single OLDI port 0
# 1 = Single OLDI port 1
# 2 = Dual OLDI 
# 3 = Dual OLDI Swap
OLDIEnabled[3] = 2

# Select MAPSEL Setting for port 0 and port 1 (Ignored for RGB mode)
# 0 = MAPSEL = L (LSB on D3/D4)
# 1 = MAPSEL = H (MSB on D3/D4)
MAPSEL0[3] = 1
MAPSEL1[3] = 1

# Set OLDI Bits Per Pixel for port 0 and 1 (Ignored in RGB mode)
# Options: 18, 24, 30
OLDIBpp0[3] = 24
OLDIBpp1[3] = 24

# Set RGB mode Bits Per Pixel (Ignored in OLDI mode)
RGBBpp[3] = 24

# Select video source for OLDI/RGB output 
# Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. 
# For Dual OLDI, use same stream for both ports
# OLDI_Port1_Source is ignored for single OLDI port 0 or RGB mode
# OLDI_RGB_Port0_Source is ignored for single OLDI port 1 mode
# 0 = Stream 0
# 1 = Stream 1
# 2 = Stream 2
# 3 = Stream 3
OLDI_RGB_Port0_Source[3] = 3
OLDI_Port1_Source[3] = 3

0 Ryan yan 2 天前回复 Links

Prodigy 40 points

您好，现在UB983可以看到时序了，但屏幕仍未出图，怀疑是983到984的链路有问题，该怎么分析呢

----------------------------------
Lock / Link Status
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x0
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x0
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x0
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x0
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x0
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x0
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x0
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x0
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x0
Ser Reg 0xC =  0x53 , Des Reg 0x53 =  0xa4 , Des Reg 0x54 =  0xc5 , Des Reg 0x4E =  0x0
----------------------------------
VP Status
VP_STATUS: 3 , VP_INTERRUPTS: 9
VP_STATUS: 2 , VP_INTERRUPTS: 9
VP_STATUS: 3 , VP_INTERRUPTS: 9
VP_STATUS: 2 , VP_INTERRUPTS: 9
VP_STATUS: 2 , VP_INTERRUPTS: 9
VP_STATUS: 3 , VP_INTERRUPTS: 9
VP_STATUS: 3 , VP_INTERRUPTS: 9
VP_STATUS: 3 , VP_INTERRUPTS: 9
VP_STATUS: 3 , VP_INTERRUPTS: 9
VP_STATUS: 2 , VP_INTERRUPTS: 9
----------------------------------
DPRX Status
540 Rate
2 Lanes
0x377
0x0
0x14
0x0
Video source is set to SST mode
----------------------------------
H Res
2560
H POL
0
H SYNC WIDTH
60
H BACK PORCH
60
H TOTAL
2768
V Res
1600
V POL
0
V SYNC WIDTH
2
V BACK PORCH
18
HV TOTAL
1652
MSA_MISC0
33
MSA_MISC1
64
MSA_MVID
28260
MSA_NVID
55621
MSA_VBID
16
SYMBOL ERRORs - Lane 0
0x80000000L
SYMBOL ERRORs - Lane 1
0xc000000
SYMBOL ERRORs - Lane 2
0x0
SYMBOL ERRORs - Lane 3
0x0
----------------------------------
Des FIFO =  0x0
----------------------------------
DTG Port 0 Timing:
Htotal =  0
Vtotal =  0
Hactive =  61503
Vactive =  0
Hstart =  0
Hsync =  0
Vsync =  0
Vback =  0
Vfront =  0
----------------------------------
Print Des MSAs

('Port', 1, ': DPTX VIDEO RESOLUTION:')
('Port', 1, ': htotal (0x180) = 2768')
('Port', 1, ': vtotal (0x184) = 0')
('Port', 1, ': hres (0x18C) = 0')
('Port', 1, ': vres (0x190) = 0')
('Port', 1, ': hstart (0x19C) = 0')
('Port', 1, ': vstart (0x1A0) = 0')
('Port', 1, ': hswidth (0x18C) = 0')
('Port', 1, ': vswidth (0x18C) = 0')
-------------------------
Ux983_APB_dump
0x0 0x1
0x4 0x64
0x8 0x0
0xc 0x0
0x10 0x0
0x14 0x0
0x18 0x14
0x1c 0x14
0x20 0x0
0x24 0x0
0x28 0x2f
0x2c 0x0
0x30 0x0
0x34 0x0
0x38 0x1
0x3c 0x0
0x40 0x0
0x44 0x70
0x48 0x0
0x4c 0x0
0x50 0x0
0x54 0x0
0x58 0x0
0x5c 0x0
0x60 0x0
0x64 0x0
0x68 0x0
0x6c 0x0
0x70 0x2
0x74 0x14
0x78 0x0
0x7c 0x0
0x80 0x1
0x84 0x0
0x88 0x0
0x8c 0x0
0x90 0x0
0x94 0x0
0x98 0x0
0x9c 0x0
0xa0 0x0
0xa4 0x0
0xa8 0x5
0xac 0x0
0xb0 0x0
0xb4 0x0
0xb8 0x0
0xbc 0x0
0xc0 0x0
0xc4 0x0
0xc8 0x0
0xcc 0x0
0xd0 0x0
0xd4 0x0
0xd8 0x1f02
0xdc 0x0
0xe0 0x0
0xe4 0x0
0xe8 0x0
0xec 0x2
0xf0 0x0
0xf4 0x0
0xf8 0x123404
0xfc 0xb0507
0x100 0x0
0x104 0x0
0x108 0x0
0x10c 0x0
0x110 0x0
0x114 0x2
0x118 0x0
0x11c 0x0
0x120 0x0
0x124 0x0
0x128 0x0
0x12c 0x0
0x130 0x0
0x134 0x0
0x138 0x0
0x13c 0x0
0x140 0x0
0x144 0x0
0x148 0x0
0x14c 0x0
0x150 0x0
0x154 0x0
0x158 0x0
0x15c 0x0
0x160 0x0
0x164 0x0
0x168 0x0
0x16c 0x0
0x170 0x0
0x174 0x0
0x178 0x0
0x17c 0x0
0x180 0xfffffffeL
0x184 0x0
0x188 0x0
0x18c 0x310183
0x190 0x59
0x194 0x0
0x198 0x79
0x19c 0x0
0x1a0 0x7f
0x1a4 0x0
0x1a8 0x7f
0x1ac 0x0
0x1b0 0x0
0x1b4 0x0
0x1b8 0x0
0x1bc 0x0
0x1c0 0x0
0x1c4 0x0
0x1c8 0x0
0x1cc 0x0
0x1d0 0x0
0x1d4 0x0
0x1d8 0x0
0x1dc 0x0
0x1e0 0x0
0x1e4 0x0
0x1e8 0x0
0x1ec 0x0
0x1f0 0x0
0x1f4 0x0
0x1f8 0x0
0x1fc 0x0
0x200 0x0
0x204 0x0
0x208 0xf03f0
0x20c 0x0
0x210 0x0
0x214 0x2
0x218 0x0
0x21c 0x0
0x220 0x0
0x224 0x0
0x400 0x14
0x404 0x2
0x408 0x1
0x40c 0x0
0x410 0x0
0x414 0x0
0x418 0x0
0x41c 0x0
0x420 0x0
0x424 0x0
0x428 0x0
0x42c 0x0
0x430 0x0
0x434 0x1
0x438 0x2
0x43c 0x377
0x440 0x0
0x444 0x0
0x448 0x0
0x44c 0x0
0x450 0x0
0x454 0x1010000
0x458 0x0
0x45c 0x0
0x460 0x0
0x464 0x0
0x468 0x0
0x46c 0x0
0x470 0x0
0x474 0x0
0x478 0x0
0x47c 0x0
0x480 0x0
0x484 0x3f3f
0x488 0x0
0x48c 0xc00
0x490 0x80000000L
0x494 0x80000000L
0x498 0x0
0x49c 0x0
0x4a0 0x0
0x4a4 0x0
0x4a8 0x0
0x4ac 0x0
0x4b0 0x0
0x4b4 0x0
0x4b8 0x0
0x4bc 0x0
0x4c0 0x0
0x4c4 0x0
0x4c8 0x0
0x4cc 0x0
0x4d0 0x0
0x4d4 0x0
0x4d8 0x0
0x4dc 0x0
0x4e0 0x0
0x4e4 0x0
0x4e8 0x0
0x4ec 0x0
0x4f0 0x0
0x4f4 0x0
0x4f8 0x0
0x4fc 0x0
0x500 0xa00
0x504 0x0
0x508 0x3c
0x50c 0x78
0x510 0xad0
0x514 0x640
0x518 0x0
0x51c 0x2
0x520 0x14
0x524 0x674
0x528 0x21
0x52c 0x40
0x530 0x6e64
0x534 0xd945
0x538 0x10
0x53c 0x0
0x700 0x0
0x704 0x0
0x708 0x0
0x70c 0x0
0x710 0x0
0x714 0x0
0x718 0x0
0x71c 0x0
0x720 0x0
0x800 0x0
0x804 0x0
0x808 0x0
0x80c 0x0
0x810 0x0
0x814 0x270
0x818 0x0
0x81c 0x2
0x820 0x90
0x824 0x270
0x828 0x0
0x82c 0x0
0x830 0x0
0x834 0x0
0x838 0x0
0x83c 0x0
0x840 0x0
0x844 0x0
0x848 0x0
0x84c 0x0
0x850 0x0
0x854 0x0
0x858 0x0
0x85c 0x0
0x860 0x0
0x864 0x0
0x868 0x0
0x86c 0x0
0x870 0x0
0x874 0x0
0x878 0x0
0x87c 0x0
0x880 0x0
0x884 0x0
0x888 0x0
0x88c 0x0
0x890 0x0
0x894 0x0
0x898 0x0
0x89c 0x0
0x8a0 0x0
0x8a4 0x0
0x8a8 0x0
0x8ac 0x0
0x8b0 0x0
0x8b4 0x0
0x8b8 0x0
0x8bc 0x0
0x8c0 0x0
0x8c4 0x0
0x8c8 0x0
0x8cc 0x0
0x8d0 0x0
0x8d4 0x0
0x8d8 0x0
0x8dc 0x0
0x8e0 0x0
0x8e4 0x0
0x8e8 0x0
0x8ec 0x0
0x8f0 0x0
0x8f4 0x0
0x8f8 0x0
0x8fc 0x0
0x900 0x0
0x904 0x0
0x908 0xc
0x90c 0x0
0x910 0x0
0x914 0x0
0x918 0x0
0x91c 0xc0000
0x920 0x0
0x924 0x0
0x928 0x0
0x92c 0x0
0x930 0x0
0x934 0x0
0xa00 0x1
0xa04 0x4
0xa08 0x0
0xa0c 0x0
0xa10 0x0
0xa14 0x1
0xa18 0x1
0xa1c 0x8
0xa20 0xf
0xa24 0x1ff003f
0xa28 0x20
0xa2c 0x0
0xa30 0x78
0xa34 0x0
0xa38 0x0
0xa3c 0x0
0xa40 0x0
0xa44 0xc
0xa48 0x0
0xa4c 0x0
0xa50 0x0
0xa54 0x0
0xa58 0x0
0xa5c 0xc000000
0xa60 0x0
0xa64 0x0
0xa68 0x0
0xa6c 0x0
0xa70 0x0
0xa74 0x0
0xa78 0x0
0xa7c 0x0
0xa80 0x1
0xa84 0x0
0xa88 0x0
0xa8c 0x18
0xa90 0x4
0xa94 0x0
0xa98 0x0
0xa9c 0x76543210
0xaa0 0x0
0xaa4 0x0
0xaa8 0x0
0xaac 0x0
0xab0 0x0
0xab4 0x1
0xab8 0x0
0xabc 0x0
0xac0 0x0
0xac4 0x0
0xac8 0x0
0xacc 0x0
0xad0 0x0
0xad4 0x0
0xad8 0x0
0xadc 0x0
0xae0 0x0
0xae4 0x0
0xae8 0x2
0xaec 0x0
0xaf0 0x0
0xaf4 0x0
0xaf8 0x0
0xafc 0xc
0xb00 0x0
0xb04 0x4
0xb08 0x0
0xb0c 0x0
0xb10 0x0
0xb14 0x0
0xb18 0x0
0xb1c 0x8
0xb20 0xf
0xb24 0x1ff003f
0xb28 0xf000f
0xb2c 0x0
0xb30 0x78
0xb34 0x0
0xb38 0x0
0xb3c 0x0
0xb40 0x0
0xb44 0x0
0xb48 0x0
0xb4c 0x0
0xb50 0x0
0xb54 0x0
0xb58 0x0
0xb5c 0x0
0xb60 0xc
0xb64 0x0
0xb68 0x0
0xb6c 0x0
0xb70 0x0
0xb74 0x0
0xb78 0x0
0xb7c 0x0
0xb80 0x0
0xb84 0x1
0xb88 0x0
0xb8c 0x0
0xb90 0x0
0xb94 0x0
0xb98 0x0
0xb9c 0x0
0xba0 0x0
0xba4 0x0
0xba8 0x0
0xbac 0x0
0xbb0 0x0
0xbb4 0x0
0xbb8 0x0
0xbbc 0x0
0xbc0 0x0
0xbc4 0x0
0xbc8 0x0
0xbcc 0x0
0xbd0 0x0
0xbd4 0x0
0xbd8 0x0
0xbdc 0x0
0xbe0 0x0

接口

接口论坛

DS90UB983-Q1: 使用UB984打pattern屏幕未出图，查看0xE8、0xE9、0xEA等寄存器发现没有training，但是硬件上HPD是高的。请问984有相关的寄存器可以改变HPD的状态，强行training吗