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您好，datasheet中有对几种不同输出的描述：非relicate mode下，输出可以是1 CLK lane+4 data lane/ 2CLK lane+2 data lane.
关于2CLK lane+2 data lane， 我再确认下是否UB954 支持CLK0+data 2，3， CLK1+data0，1 的output mode。
Receive data is CSI-2 configured with DPHY outputs as one differential clock lane (CSI_CLK0P/N) and up to four differential data lanes (CSI_D0P/N: CSI_D3P/N) or two clock lanes (CSI_CLK0P/N, CSI_CLK1P/N) and two differential data lanes for each clock. When in replicate mode data lanes CSI_D2P/N and CSI_D3P/N are associated with clock lane CSI_CLK1P/N to provide the replicated output.
