SN65DPHY440SS: SN65DPHY440SS的ESD和眼图问题协助

Dear TI FAE
上面的两个问题请帮忙关注一下，谢谢！

dear TI fae：
他的意思是指我们前端mipi clk的速率太低了，在50-450M以内不能受SN65DPHY控制吗，我们把前端mipi clk调整到450M或者以上是否就可以通过SN65DPHY控制增益？
帮忙回复，谢谢！

The failed test is AC Common-Mode Signal Level Variations between 50 and 450 MHz which can't be controlled by the DPHY440. 

这句话的意思是测试失败是50至450 MHz之间的AC共模信号电平变化，这无法由DPHY440控制。

不是指前端mipi clk的速率太低，应该是指交流信号的共模信号变化太大。

Dear Amy:
我这边再详细说明一下我这边遇到的问题，请把忙解决或者给出建议，谢谢。
项目简要描述：台式收银机双屏显示，CPU是联发科 MT8365（i350）,因主屏占用了平台mipi接口，所以副屏显示实现方案是CPU dpi（rgb 8bit dual edge）to dsi mipi（转换IC使用的是lontium LT9211_U5，放在主板端），但是由于结构ID限制，主板离副屏接口距离较远（约300mm）,所以在副屏小板上增加了TI SN65DPHY440SS，用于增强RX EQ，调整HS data/clk 的rise ,fall timing，以实现调整mipi效果增强传输距离的功能。
备注：1 .线缆采用的是双绞线（170mm），FPC及PCB都做了100Ω±10%的阻抗匹配：
           2. 由于之前解决ESD问题，现采用的是I2C模式。
遇到的问题：测试信号完整性 mipi eyes fail，下述报告中常报的fail项，请帮忙解释并给出修改建议，附件会上传相应的测试报告及规格书，请查收。
我司测试仪器使用的是Keysight MSOS804A Mixed signal Oscilloscope"（8 GHZ  20GSa/s 10-bit ADC）， D9020DPHC MIPI D-PHY Test（version：3.73.1.0），CTS version：V1.0，continue clk.
1）1.3.11{HS Data TX 20%-80% Rise Time (tR)} ,1.3.12{ HS Data TX 80%-20% Fall Time (tF)} 报错fail，是否可以修改TI-SN65DPY的0X0B寄存器来改善，请查阅测试报告给出寄存器修改值。
2）1.4.9 {HS Clock TX Common-Level Variations Between 50-450MHz(VCMTX(LF))}，1.4.4 {HS Clock TX Differential Voltage(VOD0 Pulse)}，1.4.4{HS Clock TX Differential Voltage(VOD1Pulse)}，1.4.5 {HS Clock TX Differential Voltage Mismatch (Pulse)}报错fail，这四项是否可以通过修改TI-SN65dphy的0X0E寄存器来改善，请查阅测试报告给出寄存器修改值。
3）1.4.11{HS Clock TX 20%-80% Rise Time (tR)}，1.4.12{HS Clock TX 80%-20% Fall Time (tF)}报错fail，是否可以修改TI-SN65DPY的0X0A寄存器来改善，请查阅测试报告给出寄存器修改值。
4）1.5.4{Data to Clock Skew(TSKEW(TX))(Max,Min)，1.5.4{Data to-Clock Skew(TSKEW(TX))(Mean)}，这两项体现的是什么？调整HS data/clk 的rate后是否会有改善，请请查阅测试报告给出修改建议。
以上问题请重点关注，及时反馈，谢谢！
LT9211_Datasheet_R2.5.pdfMIPI D-PHY Device 1_Report_2021-12-16_1126软件修改花屏+线束包铜箔.pdf

感谢您对TI产品的关注！为更加有效地解决您的问题，我们建议您将问题发布在E2E英文技术论坛上，将由资深的英文论坛工程师为您提供帮助。

英文论坛对应子论坛链接:https://e2e.ti.com/support/interface-group/interface/f/interface-forum

能否帮忙转达？

抱歉，我再回复的时候想点“回复”错点成了“认为已解决”

可以帮助转达，如果我将问题转换为英文，我怕表达问题的意思不到位，您可以用英文描述您的问题吗？

Dear TI FAE：
I will elaborate on the problems I encountered here, please solve them or give suggestions, thank you.
Brief description of the project: Desktop cash register dual-screen display, CPU is MediaTek MT8365 (i350), because the main screen occupies the platform mipi interface, so the secondary screen display implementation solution is CPU dpi (rgb 8bit dual edge) to dsi mipi (used by the conversion IC It is lontium LT9211_U5, placed on the motherboard side), but due to the structure ID limitation, the motherboard is far from the secondary screen interface (about 300mm), so TI SN65DPHY440SS is added to the secondary screen small board to enhance RX EQ and adjust HS data The rise and fall timing of /clk are used to adjust the mipi effect and enhance the transmission distance.
Remarks: 1. The cable uses a twisted pair (170mm), and the FPC and PCB are matched with 100Ω±10% impedance；
2. As the ESD problem was solved before, I2C mode is now adopted.
Encountered problems: test signal integrity mipi eyes fail, the frequently reported fail items in the following report, please help explain and give suggestions for modification, the attachment will upload the corresponding test report and specification, please check it.
Our test instrument uses Keysight MSOS804A Mixed signal Oscilloscope" (8 GHZ 20GSa/s 10-bit ADC), D9020DPHC MIPI D-PHY Test (version: 3.73.1.0), CTS version: V1.0, continue clk.
1) 1.3.11{HS Data TX 20%-80% Rise Time (tR)} ,1.3.12{HS Data TX 80%-20% Fall Time (tF)} reports an error failure, can I modify the 0X0B of TI-SN65DPY Register to improve, please refer to the test report to give the modified value of the register.
2) 1.4.9 {HS Clock TX Common-Level Variations Between 50-450MHz(VCMTX(LF))}, 1.4.4 {HS Clock TX Differential Voltage(VOD0 Pulse)}, 1.4.4{HS Clock TX Differential Voltage( VOD1Pulse)}, 1.4.5 {HS Clock TX Differential Voltage Mismatch (Pulse)} error fail, whether these four items can be improved by modifying the 0X0E register of TI-SN65dphy, please refer to the test report to give the modified value of the register.
3) 1.4.11{HS Clock TX 20%-80% Rise Time (tR)}, 1.4.12{HS Clock TX 80%-20% Fall Time (tF)} reports an error failure, can I modify the 0X0A of TI-SN65DPY Register to improve, please refer to the test report to give the modified value of the register.
4) 1.5.4 {Data to Clock Skew(TSKEW(TX))(Max,Min), 1.5.4{Data to-Clock Skew(TSKEW(TX))(Mean)}, what do these two items reflect? Whether there will be any improvement after adjusting the rate of HS data/clk, please refer to the test report and give suggestions for modification.
Please pay attention to the above questions and give feedback in time, thank you!

补充一下规格书及测试报告
8176.MIPI D-PHY Device 1_Report_2021-12-16_1126软件修改花屏+线束包铜箔.pdf4035.LT9211_Datasheet_R2.5.pdf

Hi Arron, 已转发，见下面链接：

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1064002/sn65dphy440ss-some-issues

Hi，Amy:
国外FAE 说关于以上问题有发邮件给您，帮忙转发一下，谢谢.