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The DP159 as a DP re-timer is intended for the sink side with Xilinx FPGA, it was not intended to be used on the source side since DP159 TX output is not compliant to the DP spec.
can you show me the answer for the following questions？
1、What is the typical time for DP159 to complete the PLL locked and what is the maximum recommended wait time, do you need to re-configure the DP159 once without the PLL locked?
2、Power up occasionally, display No Signal, grab MCU configuration DP159 IIC data, find lock_complete status reading DP159, The result is 0xE3, locked state, but not shown, the display always sends the unplug signal of HPD. The MCU is still not able to be displayed over and over again, is this a DP159 abnormal state?
3、Xilinx has a C file for configuring DP159, xdprss_dp159.c, xdprss_dp159.h is attached. The configuration flow is basically as recommended in the specification. However, some of the configuration register types vary from stage to stage and require field support to explain the functionality and impact, especially the meaning of the configuration register for DP159.
4、The DP159 register configuration recommended by the specification has only one read-back register lock_complete status for status confirmation, all other writes, how to ensure successful register configuration. Can lock_complete status be set to consider provisioning successful?
5.datarate, lane count, sink removal or DP Source no longer detected. Recommended to configure some of the registers. If the registers are completely reconfigured once (equivalent to power-up initialization), there is a problem. Is there any negative impact to the proper operation of this power up of DP159?
