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HI,
Can we please ask the customer to switch to TDP142 or DP141? DP159 is not the right solution for this design.
For the question in the spreadsheet, have they also reached out to Xilinx support? Xilinx implements the SW code base on their DP15 and Xilinx FPGA design, but I honestly don't know the purpose of these code implementations.
Do they also have a AUX log file that captures the link training between the source and the sink?
Thanks
David