• 状态 TI Thinks Resolved
  • 已锁定 已锁定
  • 回复 3 回复
  • 答案 1 答案
  • 订户 15 订户
  • 视图 326 视图
  • 用户 0 会员在此处
选项
选项
相关

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN75LVPE3410: The PCIE communication bandwidth between XILINX KU060 and X86 has been reduced from X4 to X1

meixiang dong
Prodigy 10 points
Part Number: SN75LVPE3410

1、Communication between XILINX KU060 and X86 is conducted via PCIE. Due to the long layout routing, buffer(SN75LVPE3410) is adopted for enhanced driving

2、Due to the excessive length of the wiring harness, two SN75LVPE3410s were added in the middle of the link

3、the settings of the buffer are as shown in the above figure.The result is that the PCIE bandwidth is reduced from X4 to X1

I want to know if there is anything wrong with this design!