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芯片输出的上升和下降沿时间和外部负载的容性有关,数据手册“7.3.3 Output Load Considerations”和“8.4.1 Layout Guidelines”有相关介绍。
与芯片本身传输特性相关的电容如图所示(数据手册第7页)。
请参考下面文档 “5 考虑集总电容” 的测试结果。