[参考译文] AM263P4：外部计时器触发功能(脉冲计数器)

有关代码参考、您可以使用此处提供的 PRU 代码： github.com/.../main.asm

Donovan,  

此应用可以接受任何路由到 LP-AM263P 上 BoosterPack 接头的 PR0_PRU0_GPIOx 引脚。 PR0_PRU0_GPIOx 信号通过板载多路复用器进行路由、因此务必首先为适当的路由配置多路复用器。  

如果您对配置板载多路复用器以路由 PR0_PRU0_GPIOx 引脚有任何其他问题、请告诉我。 您可以参阅此处的原理图：

https://www.ti.com/lit/zip/sprr503

此致、

Brennan

Donovan,

I2C 控制型 IO 扩展器(控制多路复用器选择线路所需)的源代码和 API 头文件可以在 C：\ti\mcu_plus_sdk_am263px_10_00_00_35\source\board\ioexp 中找到。 确保您查看 TCA6416文件、这是 LP-AM263P 上 IO 扩展器的器件型号。

此致、

Brennan

您好、  

抱歉、您的回复延迟、我们错过了此 e2e 主题、因为您将其标记为"已解决"。如果您有任何后续问题、请创建新的 e2e 主题、以避免混淆。

您可以在下面找到 PRU 代码、它有2种方法在达到脉冲计数时从 PRU 触发到 R5F 的中断、并在注释中回答您的问题

如果您需要任何帮助、请告诉我们。

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;************************************************************************************
;   File:     main.asm
;
;   Brief:    Template asm file example
;************************************************************************************

; CCS/makefile specific settings
    .retain     ; Required for building .out with assembly file
    .retainrefs ; Required for building .out with assembly file

    .global     main
    .sect       ".text"

;************************************* includes *************************************
    .include    "icss_pin_macros.inc"
    .include    "icss_iep_regs.inc"
    .include    "icss_iep_macros.inc"

    .asg	R2,	   CUR_PULSE_COUNT
    .asg    R3,    TOT_PULSE_COUNT
    .asg    R4,    TEMP_REG1

FILTER_CYCLES       .set       3
PRU_PIN             .set       0


m_wait_for_cap6_rise    .macro
    ;wait until cap6 rise event
wait?:
    lbco        &TEMP_REG1, ICSS_IEP_CONST, ICSS_IEP_CAP_STATUS_REG, 4
    qbbc         wait?, TEMP_REG1, 6    
    ;read cap6 value to clear capture status
    lbco        &TEMP_REG1, ICSS_IEP_CONST, ICSS_IEP_CAPR6_REG, 4
    .endm

;********
;* MAIN *
;********

main:

init:
;----------------------------------------------------------------------------
;   Clear the register space
;   Before begining with the application, make sure all the registers are set
;   to 0. PRU has 32 - 4 byte registers: R0 to R31, with R30 and R31 being special
;   registers for output and input respectively.
;----------------------------------------------------------------------------
; Give the starting address and number of bytes to clear.
    zero	&r0, 120
    ldi     TOT_PULSE_COUNT, 1000
    ldi     CUR_PULSE_COUNT, 0

    ;************************************************************
    ;               Polling PRU GPI(Approach 1)
    ;
    ;************************************************************

wait_for_next_pulse:
    m_wait_low_pulse    FILTER_CYCLES, PRU_PIN
    ADD     CUR_PULSE_COUNT, CUR_PULSE_COUNT, 1
    qbne    wait_for_next_pulse, CUR_PULSE_COUNT, TOT_PULSE_COUNT
    LDI     CUR_PULSE_COUNT, 0
    ;Generate interrupt to R5F(refer 7.2.5.2.2.2 of Technical reference manual for more details)
    ;pr0_pru_mst_intr[0]_intr_req ---> Host Interrupt 2 (INTC Mapping can be done from PRUICSS sysconfig module)
    ;Host Interrupt 2 ---> R5FSS0_CORE0_INTR_PRU_ICSSM0_PR1_HOST_INTR_PEND_0 (This mapping is fixed)
    ;R5FSS0_CORE0_INTR_PRU_ICSSM0_PR1_HOST_INTR_PEND_0 can be mapped to ISR(refer <sdk_path>/examples/gpio_input_interrupt)
    LDI     R30.b0, 0x20
    qba     wait_for_next_pulse     

    ;************************************************************************************************************************************
    ;               Using IEP capture mode (Approach 2)
    ;   Use IEP_CAPR6_REG0/IEP_CAPR6_REG1 which can capture time stamp of IEP on rise Edge of PRGn_IEP0_EDC_LATCH_IN0(SOC level IO signal)
    ;************************************************************************************************************************************

iep:
	; disable iep timer
    m_set_iep_global_cfg_reg   	0, TEMP_REG1, 0x20
    ; set starting count value of IEP counter
    m_set_iep_count_reg0       	0, TEMP_REG1, 0xffffffff
    m_set_iep_count_reg1       	0, TEMP_REG1, 0xffffffff
	;Enable the reset of iep counter with compare 0
	ldi     TEMP_REG1,  0x03
	sbco    &TEMP_REG1, ICSS_IEP_CONST, ICSS_IEP_CMP_CFG_REG, 4
	fill	&TEMP_REG1, 0x4
	sbco    &TEMP_REG1, ICSS_IEP_CONST, ICSS_IEP_CMP0_REG, 4
	;clear the compare status
	ldi     TEMP_REG1, 0x01
	sbco    &TEMP_REG1, ICSS_IEP_CONST, ICSS_IEP_CMP_STATUS_REG, 4
	;set cap 0 to 7 in continouous mode with External capture enable
	ldi     TEMP_REG1,  0x00
	sbco    &TEMP_REG1, ICSS_IEP_CONST, ICSS_IEP_CAP_CFG_REG, 4
	lbco    &TEMP_REG1, ICSS_IEP_CONST, ICSS_IEP_CAPR0_REG, 4
    lbco    &TEMP_REG1, ICSS_IEP_CONST, ICSS_IEP_CAPR1_REG, 4
    lbco    &TEMP_REG1, ICSS_IEP_CONST, ICSS_IEP_CAPR2_REG, 4
    lbco    &TEMP_REG1, ICSS_IEP_CONST, ICSS_IEP_CAPR3_REG, 4
    lbco    &TEMP_REG1, ICSS_IEP_CONST, ICSS_IEP_CAPR4_REG, 4
    lbco    &TEMP_REG1, ICSS_IEP_CONST, ICSS_IEP_CAPR5_REG, 4
	; Start IEP timer with increment of 5 (increment of 1->1ns)
    m_set_iep_global_cfg_reg   0, TEMP_REG1, 0x51

wait_for_next_capture_event:
    m_wait_for_cap6_rise
    ADD     CUR_PULSE_COUNT, CUR_PULSE_COUNT, 1
    qbne    wait_for_next_capture_event, CUR_PULSE_COUNT, TOT_PULSE_COUNT
    LDI     CUR_PULSE_COUNT, 0
    ;Generate interrupt to R5F(refer 7.2.5.2.2.2 of Technical reference manual for more details)
    ;pr0_pru_mst_intr[0]_intr_req ---> Host Interrupt 2 (INTC Mapping can be done from PRUICSS sysconfig module)
    ;Host Interrupt 2 ---> R5FSS0_CORE0_INTR_PRU_ICSSM0_PR1_HOST_INTR_PEND_0 (This mapping is fixed)
    ;R5FSS0_CORE0_INTR_PRU_ICSSM0_PR1_HOST_INTR_PEND_0 can be mapped to ISR(refer <sdk_path>/examples/gpio_input_interrupt)
    LDI     R30.b0, 0x20
    qba     wait_for_next_capture_event