[参考译文] AM2431：对于具有 DMA 的 MCSPI 外设、如何传输超过 4096 个字节

您好：

我不确定您要在哪个 SDK 版本上测试该应用程序。 我建议使用最新版本。 它是： https://www.ti.com/tool/download/MCU-PLUS-SDK AM243X/11.02.00.24

原因是我发现很少提交可以帮助解决您的 DMA 问题。

您可以：

 1. https://github.com/TexasInstruments/mcupsdk-core/commit/4d768588852b0bc90a30a45b6355260c443eff05#diff-57541bc9ca53109e199e08e3071a8375f7a64f5f256605dd7b84c8388baacd21

 2. https://github.com/TexasInstruments/mcupsdk-core/commit/1c562a26b166792e3e7f1ac5bb4b4a19430aeab7

还有其他变化、旨在改进整个 MCSPI 驱动器。

如果您还没有阅读本指南、还建议您阅读： e2e.ti.com/.../faq-sk-am64b-mcspi-integration-guide

此致、

Vaibhav

是的、它解决了问题。  最初、我们每个 DMA 通道最多只能传输 2048 字节的数据、因此我们考虑参考网络模块链接多个 DMA 通道的方法。 然而,后来发现这是没有必要的。 目前、我们使用单个 DMA 通道并实现了所需的功能。

尊敬的 Vaibhav：

我们直接修改了应用程序代码。 原始代码包含许多尚未整理的中间调试段、因此我提取了密钥代码。 请帮助审查我们的实施是否有任何问题。

关键战略如下：
我们添加了一个 SPI CS 上升沿中断。 在开始 DMA 发送/接收后、如果我们接收到 CS 中断而不是 SPI 完成中断、则重置 DMA 并通过以下函数 deInitMcspiSlaveDMACh () 检索已接收到的数据长度。

extern MCSPI_ChConfig       *gConfigMcspiChCfg[];
int32_t myUdmaDeInitCh(Udma_ChHandle chHandle,
                                  uint32_t  isChEnabled);
								  
								 

void terminateMcspiSlaveDMA()
{
    int32_t                retVal;
    uint32_t index = 2;
    uint32_t chCnt = 0;
    uint64_t               pDesc;
    MCSPILLD_Handle        hMcspi;
    MCSPILLD_InitHandle    hMcspiInit;
    MCSPI_Config *config = NULL;
    MCSPI_Object *obj    = NULL;
    uint32_t               chNum, effByteCnt, peerData;
    MCSPI_UdmaChConfig    *dmaChConfig;
    MCSPI_Transaction     *transaction;
    CSL_UdmapCppi5HMPD    *pHpd;
    MCSPI_ChObject        *chObj;
    uint32_t               baseAddr, irqStatus = 0U;
    Udma_ChHandle          rxChHandle, txChHandle;
    int32_t                status = MCSPI_STATUS_SUCCESS;
    uint8_t *pRxHpdMem, *pTxHpdMem;
    MCSPI_ChConfig      *chConfig;

    config = &gMcspiConfig[index];
    obj = config->object;
    hMcspi = obj->mcspiLldHandle;
    hMcspiInit   = hMcspi->hMcspiInit;
    baseAddr     = hMcspi->baseAddr;
    transaction  = &hMcspi->transaction;
    chNum        = transaction->channel;
    chObj        = &hMcspi->hMcspiInit->chObj[chNum];
    dmaChConfig  = (MCSPI_UdmaChConfig *)chObj->dmaChCfg;
    rxChHandle   = dmaChConfig->rxChHandle;
    txChHandle   = dmaChConfig->txChHandle;
    effByteCnt   = transaction->count << chObj->bufWidthShift;
    pRxHpdMem    = dmaChConfig->rxHpdMem;
    pTxHpdMem    = dmaChConfig->txHpdMem;
    chConfig    = gConfigMcspiChCfg[index];

    hMcspi->transaction.count = 0;


	pHpd = (CSL_UdmapCppi5HMPD *)((uint8_t *) pTxHpdMem + i * sizeof(CSL_UdmapCppi5HMPD));
	CacheP_inv(pHpd, dmaChConfig->hpdMemSize, CacheP_TYPE_ALLD);

	pHpd = (CSL_UdmapCppi5HMPD *)((uint8_t *) pRxHpdMem + i * sizeof(CSL_UdmapCppi5HMPD));
	CacheP_inv(pHpd, dmaChConfig->hpdMemSize, CacheP_TYPE_ALLD);

	retVal = Udma_ringDequeueRaw(Udma_chGetCqRingHandle(txChHandle), &pDesc);
	if (retVal < 0)
		retVal = Udma_ringFlushRaw(Udma_chGetFqRingHandle(txChHandle), &pDesc);

	retVal = Udma_ringDequeueRaw(Udma_chGetCqRingHandle(rxChHandle), &pDesc);
	if (retVal < 0)
		retVal = Udma_ringFlushRaw(Udma_chGetFqRingHandle(rxChHandle), &pDesc);
	else
	{
		pHpd   = (CSL_UdmapCppi5HMPD *)(uintptr_t)pDesc;
		if (retVal == UDMA_SOK)
		{
			status = MCSPI_TRANSFER_COMPLETED;
		}
		else
		{
			status = MCSPI_TRANSFER_FAILED;
			//hMcspi->hMcspiInit->errorCallbackFxn(hMcspi, status);
		}

		if ((status == MCSPI_TRANSFER_COMPLETED) &&
			(MCSPI_TR_MODE_TX_ONLY != chObj->chCfg->trMode))
		{
			if(dmaChConfig->isCqRingMem != UDMA_COMP_QUEUE_RING_MEM_ENABLED){
				retVal = Udma_getPeerData(rxChHandle, &peerData);
				DebugP_assert(retVal == UDMA_SOK);
	//            startTicks = hMcspiInit->clockP_get();
	//                    while ((effByteCnt != peerData) && (elapsedTicks < transaction->timeout))
	//                    {
	//                        retVal += Udma_getPeerData(rxChHandle, &peerData);
	//                        elapsedTicks = hMcspiInit->clockP_get() - startTicks;
	//                    };
				/* Clear Data */
				retVal += Udma_clearPeerData(rxChHandle, peerData);
			}
			DebugP_assert(retVal == UDMA_SOK);


			/* Get Byte count received */
			effByteCnt = (pHpd->descInfo & CSL_UDMAP_CPPI5_PD_DESCINFO_PKTLEN_MASK) >> CSL_UDMAP_CPPI5_PD_DESCINFO_PKTLEN_SHIFT;
			hMcspi->transaction.count += (effByteCnt >> chObj->bufWidthShift);
		}
	}


    /* Stop MCSPI Channel */
    MCSPI_lld_dmaStop(hMcspi, chObj, chNum);
    hMcspi->state = MCSPI_STATE_READY;

    irqStatus = CSL_REG32_RD(baseAddr + CSL_MCSPI_IRQSTATUS);
    if ((irqStatus & ((uint32_t)CSL_MCSPI_IRQSTATUS_RX0_OVERFLOW_MASK)) != 0U)
    {
      retVal = MCSPI_TRANSFER_CANCELLED;
      hMcspi->errorFlag |= MCSPI_ERROR_RX_OVERFLOW;
    }

    if (((irqStatus & ((uint32_t)CSL_MCSPI_IRQSTATUS_TX0_UNDERFLOW_MASK << (4U * chNum))) != 0U) &&
      ((hMcspiInit->msMode == MCSPI_MS_MODE_PERIPHERAL)))
    {
      retVal = MCSPI_TRANSFER_CANCELLED;
      hMcspi->errorFlag |= MCSPI_ERROR_TX_UNDERFLOW;
    }

    if(hMcspi->errorFlag != 0U)
    {
      hMcspi->hMcspiInit->errorCallbackFxn(hMcspi, retVal);
    }
    else
    {
      hMcspi->hMcspiInit->transferCallbackFxn(hMcspi, MCSPI_TRANSFER_COMPLETED);
    }

}


//disable DMA Channel
int32_t myUdmaDeInitCh(Udma_ChHandle chHandle,
                                  uint32_t  isChEnabled)
{
    int32_t udmaStatus = UDMA_SOK;
    int32_t status = MCSPI_STATUS_SUCCESS;

    if(isChEnabled == MCSPI_UDMA_CHANNEL_ENABLE)
    {
        /* Disable Channel */
        udmaStatus = Udma_chDisable(chHandle, UDMA_DEFAULT_CH_DISABLE_TIMEOUT);
        DebugP_assert(UDMA_SOK == udmaStatus);
    }

    if(udmaStatus == UDMA_SOK)
    {
        status = MCSPI_STATUS_SUCCESS;
    }
    else
    {
        status = MCSPI_STATUS_FAILURE;
    }


    return status;
}

//disable DMA Channel TX
int32_t myUdmaDeInitChTX(Udma_ChHandle chHandle,
                                  uint32_t  isChEnabled)
{
    Udma_DrvHandleInt   drvHandle;
    CSL_PktdmaRT        pktdmaRtStatus;
    Udma_ChHandleInt    chHandleInt = (Udma_ChHandleInt) chHandle;

    drvHandle = chHandleInt->drvHandle;

    /*
     *  TRT_CTL Bit31 TX_ENABLE
     *  This field enables or disables the channel. Disabling a channel
        halts operation on the channel after the current block transfer is
        completed. Disabling a channel in the middle of a packet transfer
        may result in underflow conditions in the attached application block
        and data loss. When a channel is disabled, the implementation may
        choose to reset all state for the channel. The pause bit should
        be asserted instead of clearing enable directly if the intent is to
        temporarily pause the channel. This field is encoded as follows: 0 =
        channel is disabled 1 = channel is enabled This field will be cleared
        by HW after a teardown is requested to indicate that the channel
        teardown is complete.
     * */
    pktdmaRtStatus.enable   = FALSE;
    pktdmaRtStatus.teardown = FALSE;
    pktdmaRtStatus.forcedTeardown = FALSE;

    (void) CSL_pktdmaSetTxRT(&drvHandle->pktdmaRegs, chHandleInt->txChNum, &pktdmaRtStatus);

    return UDMA_SOK;
}

int32_t deInitMcspiSlaveDMACh()
{
    int32_t              status = SystemP_SUCCESS;
    uint32_t index = 2;
    MCSPI_ChConfig      *chConfig;
    MCSPI_Config        *config = NULL;
    MCSPI_Object        *obj    = NULL;
    MCSPILLD_Handle      mcspiLldHandle;
    uint32_t chCnt = 0;
    MCSPI_ChObject      *chObj;
    MCSPI_UdmaChConfig  *dmaChConfig;

    config = &gMcspiConfig[index];
    obj = config->object;
    mcspiLldHandle                = obj->mcspiLldHandle;

    chConfig    = gConfigMcspiChCfg[index];

    chObj            = &mcspiLldHandle->hMcspiInit->chObj[chCnt];
    dmaChConfig      = (MCSPI_UdmaChConfig *)chObj->dmaChCfg;

    myUdmaDeInitCh(dmaChConfig->rxChHandle, dmaChConfig->isChEnabled);

    myUdmaDeInitChTX(dmaChConfig->txChHandle, dmaChConfig->isChEnabled);

    terminateMcspiSlaveDMA();

    return status;
}

尊敬的 Vaibhav：

如下所示、 在 SYSCFG 中、MCSPI 配置为轮询模式、然后在 main 函数中主动调用以下函数来初始化 DMA。