[参考译文] AM2432：PRU 固件加载将清除 TXCFG0_TX_CLK_DELAY 的寄存器

尊敬的 Zekun：

MII_RT_TXCFG0/1每次检测到端口状态更改时、EtherCAT PRU 固件都会重写完整的寄存器、包括位 30：28 (TX_CLK_DELAY)。 当端口扫描循环运行时、这会在固件初始化期间重复发生、因此任何预加载写入都会被覆盖、并且只有在固件稳定后才会“粘滞“。

推荐解决方案（无固件更改）：

设置TI_VS_PORT0_TX_START_DELAY共享 RAM 参数内的 TX_CLK_DELAY 位 在启用 PRU 内核之前 。 SDK 在 EtherCAT 协议栈初始化期间填充此参数。 在 FWD 和 REV TX_START_DELAY 16 位字的 14：12 位中包含所需的 TX_CLK_DELAY 值：

bsp_init()ESC_ADDR_TI_PROCESS_PATH_TX_START_DELAY0xE10在加载 PRU 固件之前将 TX 启动延迟写入 PRUSS Data RAM（偏移）。 当 PRU 固件启动时、它从 DRAM 中读取该字并将其写入MII_RT_TXCFG硬件寄存器。

由于存储的仅字编码TX_START_DELAY（位 9–0）且左侧位 14–12 为零、因此TX_CLK_DELAY=0, PRU 固件始终在 PRU 启动之前写入覆盖直接写入硬件寄存器的任何值。

通过对TX_CLK_DELAY写入 DRAM[]的值的位[14：12]0xE10-0xE11进行编码、PRU 固件将TX_CLK_DELAY在每次初始化MII_RT_TXCFG寄存器时自动保留正确的设置。 无需加载后写入、无需 2 秒延迟。

背景

写入ESC_ADDR_TI_PROCESS_PATH_TX_START_DELAY（PRUSS DRAM 偏移）0xE10的 16 位字直接映射到MII_RT_TXCFG硬件寄存器的位[31：16]。 两个可独立配置的字段被打包至此字中：

  Address   Byte     Bits      MII_RT_TXCFG field
  --------  -------  --------  ---------------------------
  0xE10     low      [7:0]     TX_START_DELAY[7:0]
  0xE11     high     [6:4]     TX_CLK_DELAY   (3-bit, 0–7)
                     [1:0]     TX_START_DELAY[9:8]  (always 0 for current values)

以前这些都是作为一个单一的写在一起bsp_write_word。 更改会将它们分成两个bsp_write_byte呼叫、以便分别配置和理解每个字段。

对进行了更改  tiescbsp.h

Added — new TIESC_TX_CLK_DELAY_BYTE helper and user knob:

/*
 * TX_CLK_DELAY high-byte value for ESC_ADDR_TI_*_TX_START_DELAY + 1.
 * Bits [6:4] of the high byte map to TX_CLK_DELAY bits [30:28] in MII_RT_TXCFG.
 * Adds (n*5 + 10) ns + SOC delay per step (n = 0..7).
 * NOTE: Per TRM, keep at 0h (default) for guaranteed MII_G_RT I/O timing
 * at 200/225/250 MHz core clock.
 */
#define TIESC_TX_CLK_DELAY_BYTE(n)    ((uint8_t)((n) << 4U))

/* TX_CLK_DELAY for process (forward) path: 0 = default; set to 1-7 to add MII launch delay */
#define TIESC_PROCESS_PATH_TX_CLK_DELAY    3U
Unchanged — existing TX_START_DELAY macros (now used as the low byte):

#if ENABLE_MULTIPLE_SM_ACCESS_IN_SINGLE_DATAGRAM
#define TIESC_PROCESS_PATH_TX_DELAY_200_MHZ_CLOCK    0x98
#else
#define TIESC_PROCESS_PATH_TX_DELAY_200_MHZ_CLOCK    0x48
#endif
#define TIESC_AUTOFORWARD_PATH_TX_DELAY_200_MHZ_CLOCK    0x38

#if ENABLE_MULTIPLE_SM_ACCESS_IN_SINGLE_DATAGRAM
#define TIESC_PROCESS_PATH_TX_DELAY_333_MHZ_CLOCK    0xA0
#else
#define TIESC_PROCESS_PATH_TX_DELAY_333_MHZ_CLOCK    0x50
#endif
#define TIESC_AUTOFORWARD_PATH_TX_DELAY_333_MHZ_CLOCK    0x30

对进行了更改  tiescbsp.c

Before (single 16-bit write, TX_CLK_DELAY was always 0):

bsp_write_word(pruIcssHandle, TIESC_PROCESS_PATH_TX_DELAY_200_MHZ_CLOCK,
            ESC_ADDR_TI_PROCESS_PATH_TX_START_DELAY);
bsp_write_word(pruIcssHandle, TIESC_AUTOFORWARD_PATH_TX_DELAY_200_MHZ_CLOCK,
            ESC_ADDR_TI_AUTOFORWARD_PATH_TX_START_DELAY);
After (two separate byte writes for process path):

/* Process (forward) path TX_START_DELAY: low byte of the 16-bit word at
 * ESC_ADDR_TI_PROCESS_PATH_TX_START_DELAY. Maps to MII_RT_TXCFG bits[23:16].
 * Controls the number of MII_RT clock cycles after RXDV before TX starts. */
bsp_write_byte(pruIcssHandle, TIESC_PROCESS_PATH_TX_DELAY_200_MHZ_CLOCK,
            ESC_ADDR_TI_PROCESS_PATH_TX_START_DELAY);

/* Process (forward) path TX_CLK_DELAY: high byte of the same 16-bit word.
 * Bits[6:4] map to MII_RT_TXCFG bits[30:28]. Controls the number of
 * MII_RT clock cycles to wait before launching TX data on the MII interface.
 * Configured separately so TX_START_DELAY and TX_CLK_DELAY can be tuned
 * independently. Set TIESC_PROCESS_PATH_TX_CLK_DELAY (0-7) in tiescbsp.h. */
bsp_write_byte(pruIcssHandle, TIESC_TX_CLK_DELAY_BYTE(TIESC_PROCESS_PATH_TX_CLK_DELAY),
            ESC_ADDR_TI_PROCESS_PATH_TX_START_DELAY + 1U);

/* Autoforward path TX_START_DELAY: written as a single 16-bit word.
 * TX_CLK_DELAY is not configured for the autoforward path (kept at 0). */
bsp_write_word(pruIcssHandle, TIESC_AUTOFORWARD_PATH_TX_DELAY_200_MHZ_CLOCK,
            ESC_ADDR_TI_AUTOFORWARD_PATH_TX_START_DELAY);
The same pattern applies for the 333 MHz branch.

如何配置 TX_CLK_DELAY

在中仅更改这一行tiescbsp.h：

#define TIESC_PROCESS_PATH_TX_CLK_DELAY    3U   /* 0 = default; 1–7 = additional delay */

自动转发路径特意保留为bsp_write_word没有TX_CLK_DELAY组件（自动转发路径具有更严格的延迟要求）。

文件已更改摘要

附加更新的文件以供参考。 确保重建 FWHAL： e2e.ti.com/.../0143.tiescbsp.c e2e.ti.com/.../tiescbsp.h

请注意、这些更改是相对于进行的 工业通信 SDK 2025.00.08 。

此致、
Aaron