[参考译文] TMS570LC4357：HAL 代码生成器 example_mibspiDMA 扩展到4个 mibSPI、每个都有1个传输组(mibSPI4在接收区域中有损坏的数据)

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Other Parts Discussed in Thread: HALCOGEN

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1047943/tms570lc4357-hal-code-generator-example_mibspidma-extended-to-4-mibspis-with-1-transfer-group-each-mibspi4-has-corrupted-data-in-receive-area

器件型号：TMS570LC4357
主题中讨论的其他器件：HALCOGEN

HAL 代码发生器版本04.07.01

CCS 版本10.4.0.00006

将 HALCoGen 示例 example_mibspiDMA 扩展到四个 mibSPI (mibSPI1、mibSPI2、mibSPI3、mibSPI4)。每个 MibSPI 在环回模式下运行并传输1024个字。针对每个从 RAM 位置到传输组的 MibSPI、通过 DMA 执行数据传输列表、反之亦然。请参阅下面随附的代码。使用调试器运行代码显示、在 RAM 位置 RXDATA4中接收到的数据在某种程度上不同于传输 RAM 位置 TXDATA4中设置的数据。每个 mibSPI 的 SPI 时钟被设定为25MHz。 mibSPI1、2和3的接收数据看起来不错。为了处理大数据、我还扩展了示例中给出的函数 mibspiDmaConfig。

我需要帮助来解决这个问题！

/* USER CODE BEGIN (0) */
/* USER CODE END */

/* Include Files */

#include "HL_sys_common.h"

/* USER CODE BEGIN (1) */
#include "HL_mibspi.h"
#include "HL_sys_dma.h"

/* example data Pattern configuration */
#define D_SIZE      128
#define BUFFER_SIZE 1024

void loadDataPattern(uint32 psize, uint16* pptr);
void mibspiEnableInternalLoopback(mibspiBASE_t *mibspi);
void dmaConfigCtrlPacket(uint32 sadd,uint32 dadd,uint32 dsize);
void mibspiDmaConfig(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel);

#pragma SET_DATA_SECTION(".sharedRAM")
uint16 TXDATA[BUFFER_SIZE];         /* transmit buffer in sys ram */
uint16 RXDATA[BUFFER_SIZE]= {0};    /* receive  buffer in sys ram */
uint16 TXDATA2[BUFFER_SIZE];         /* transmit buffer in sys ram */
uint16 RXDATA2[BUFFER_SIZE]= {0};    /* receive  buffer in sys ram */
uint16 TXDATA3[BUFFER_SIZE];         /* transmit buffer in sys ram */
uint16 RXDATA3[BUFFER_SIZE]= {0};    /* receive  buffer in sys ram */
uint16 TXDATA4[BUFFER_SIZE];         /* transmit buffer in sys ram */
uint16 RXDATA4[BUFFER_SIZE]= {0};    /* receive  buffer in sys ram */
#pragma SET_DATA_SECTION()

g_dmaCTRL g_dmaCTRLPKT1, g_dmaCTRLPKT2;    /* dma control packet configuration stack */
/* USER CODE END */

/** @fn void main(void)
*   @brief Application main function
*   @note This function is empty by default.
*
*   This function is called after startup.
*   The user can use this function to implement the application.
*/

/* USER CODE BEGIN (2) */
/* USER CODE END */

void main(void)
{
/* USER CODE BEGIN (3) */

   uint16 i;
   uint32 j;

   /* - creating a data chunk in system ram to start with ... */
   loadDataPattern(BUFFER_SIZE,&TXDATA[0]);
   loadDataPattern(BUFFER_SIZE,&TXDATA2[0]);
   loadDataPattern(BUFFER_SIZE,&TXDATA3[0]);
   loadDataPattern(BUFFER_SIZE,&TXDATA4[0]);

   /* - initializing mibspi - enabling tg 0 , length 127 (halcogen file)*/
   mibspiInit();

   /* - enabling loopback ( this is to emulate data transfer without external wires */
   mibspiEnableInternalLoopback(mibspiREG1);
   mibspiEnableInternalLoopback(mibspiREG2);
   mibspiEnableInternalLoopback(mibspiREG3);
   mibspiEnableInternalLoopback(mibspiREG4);

   /* - configuring dma control packets   */
   g_dmaCTRLPKT1.SADD      = (uint32)TXDATA;    /* source address             */
   g_dmaCTRLPKT1.DADD      = (uint32)&(mibspiRAM1->tx[0].data);    /* destination  address       */
   g_dmaCTRLPKT1.CHCTRL    = 0;                 /* channel control            */
   g_dmaCTRLPKT1.FRCNT	   = 8;//1;                 /* frame count                */
   g_dmaCTRLPKT1.ELCNT     = D_SIZE;            /* element count              */
   g_dmaCTRLPKT1.ELDOFFSET = 4;                 /* element destination offset */
   g_dmaCTRLPKT1.ELSOFFSET = 0;		            /* element destination offset */
   g_dmaCTRLPKT1.FRDOFFSET = 0;		            /* frame destination offset   */
   g_dmaCTRLPKT1.FRSOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT1.PORTASGN  = PORTA_READ_PORTB_WRITE;
   g_dmaCTRLPKT1.RDSIZE    = ACCESS_16_BIT;	    /* read size                  */
   g_dmaCTRLPKT1.WRSIZE    = ACCESS_16_BIT; 	/* write size                 */
   g_dmaCTRLPKT1.TTYPE     = FRAME_TRANSFER ;   /* transfer type              */
   g_dmaCTRLPKT1.ADDMODERD = ADDR_INC1;         /* address mode read          */
   g_dmaCTRLPKT1.ADDMODEWR = ADDR_OFFSET;       /* address mode write         */
   g_dmaCTRLPKT1.AUTOINIT  = AUTOINIT_ON;       /* autoinit                   */

   g_dmaCTRLPKT2.SADD      = (uint32)&(mibspiRAM1->rx[0].data);    /* source address             */
   g_dmaCTRLPKT2.DADD      = (uint32)RXDATA;    /* destination  address       */
   g_dmaCTRLPKT2.CHCTRL    = 0;                 /* channel control            */
   g_dmaCTRLPKT2.FRCNT	   = 8;//1;                 /* frame count                */
   g_dmaCTRLPKT2.ELCNT     = D_SIZE;             /* element count              */
   g_dmaCTRLPKT2.ELDOFFSET = 0;                 /* element destination offset */
   g_dmaCTRLPKT2.ELSOFFSET = 4;		            /* element destination offset */
   g_dmaCTRLPKT2.FRDOFFSET = 0;		            /* frame destination offset   */
   g_dmaCTRLPKT2.FRSOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT2.PORTASGN  = PORTB_READ_PORTA_WRITE;
   g_dmaCTRLPKT2.RDSIZE    = ACCESS_16_BIT;	    /* read size                  */
   g_dmaCTRLPKT2.WRSIZE    = ACCESS_16_BIT; 	/* write size                 */
   g_dmaCTRLPKT2.TTYPE     = FRAME_TRANSFER ;   /* transfer type              */
   g_dmaCTRLPKT2.ADDMODERD = ADDR_OFFSET;         /* address mode read          */
   g_dmaCTRLPKT2.ADDMODEWR = ADDR_INC1;       /* address mode write         */
   g_dmaCTRLPKT2.AUTOINIT  = AUTOINIT_ON;       /* autoinit                   */

   /* upto 32 control packets are supported. */

   /* - setting dma control packets */
   dmaSetCtrlPacket(DMA_CH0,g_dmaCTRLPKT2);
   dmaSetCtrlPacket(DMA_CH1,g_dmaCTRLPKT1);

   /* - setting the dma channel to trigger on h/w request */
   dmaSetChEnable(DMA_CH0, DMA_HW);
   dmaSetChEnable(DMA_CH1, DMA_HW);

   /* - configuring dma control packets   */
   g_dmaCTRLPKT1.SADD      = (uint32)TXDATA2;    /* source address             */
   g_dmaCTRLPKT1.DADD      = (uint32)&(mibspiRAM2->tx[0].data);    /* destination  address       */
   g_dmaCTRLPKT1.CHCTRL    = 0;                 /* channel control            */
   g_dmaCTRLPKT1.FRCNT     = 8;//1;                 /* frame count                */
   g_dmaCTRLPKT1.ELCNT     = D_SIZE;            /* element count              */
   g_dmaCTRLPKT1.ELDOFFSET = 4;                 /* element destination offset */
   g_dmaCTRLPKT1.ELSOFFSET = 0;                 /* element destination offset */
   g_dmaCTRLPKT1.FRDOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT1.FRSOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT1.PORTASGN  = PORTA_READ_PORTB_WRITE;
   g_dmaCTRLPKT1.RDSIZE    = ACCESS_16_BIT;     /* read size                  */
   g_dmaCTRLPKT1.WRSIZE    = ACCESS_16_BIT;     /* write size                 */
   g_dmaCTRLPKT1.TTYPE     = FRAME_TRANSFER ;   /* transfer type              */
   g_dmaCTRLPKT1.ADDMODERD = ADDR_INC1;         /* address mode read          */
   g_dmaCTRLPKT1.ADDMODEWR = ADDR_OFFSET;       /* address mode write         */
   g_dmaCTRLPKT1.AUTOINIT  = AUTOINIT_ON;       /* autoinit                   */

   g_dmaCTRLPKT2.SADD      = (uint32)&(mibspiRAM2->rx[0].data);    /* source address             */
   g_dmaCTRLPKT2.DADD      = (uint32)RXDATA2;    /* destination  address       */
   g_dmaCTRLPKT2.CHCTRL    = 0;                 /* channel control            */
   g_dmaCTRLPKT2.FRCNT     = 8;//1;                 /* frame count                */
   g_dmaCTRLPKT2.ELCNT     = D_SIZE;             /* element count              */
   g_dmaCTRLPKT2.ELDOFFSET = 0;                 /* element destination offset */
   g_dmaCTRLPKT2.ELSOFFSET = 4;                 /* element destination offset */
   g_dmaCTRLPKT2.FRDOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT2.FRSOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT2.PORTASGN  = PORTB_READ_PORTA_WRITE;
   g_dmaCTRLPKT2.RDSIZE    = ACCESS_16_BIT;     /* read size                  */
   g_dmaCTRLPKT2.WRSIZE    = ACCESS_16_BIT;     /* write size                 */
   g_dmaCTRLPKT2.TTYPE     = FRAME_TRANSFER ;   /* transfer type              */
   g_dmaCTRLPKT2.ADDMODERD = ADDR_OFFSET;         /* address mode read          */
   g_dmaCTRLPKT2.ADDMODEWR = ADDR_INC1;       /* address mode write         */
   g_dmaCTRLPKT2.AUTOINIT  = AUTOINIT_ON;       /* autoinit                   */

   /* upto 32 control packets are supported. */

   /* - setting dma control packets */
   dmaSetCtrlPacket(DMA_CH2,g_dmaCTRLPKT2);
   dmaSetCtrlPacket(DMA_CH3,g_dmaCTRLPKT1);

   /* - setting the dma channel to trigger on h/w request */
   dmaSetChEnable(DMA_CH2, DMA_HW);
   dmaSetChEnable(DMA_CH3, DMA_HW);

   /* - configuring dma control packets   */
   g_dmaCTRLPKT1.SADD      = (uint32)TXDATA3;    /* source address             */
   g_dmaCTRLPKT1.DADD      = (uint32)&(mibspiRAM3->tx[0].data);    /* destination  address       */
   g_dmaCTRLPKT1.CHCTRL    = 0;                 /* channel control            */
   g_dmaCTRLPKT1.FRCNT     = 8;//1;                 /* frame count                */
   g_dmaCTRLPKT1.ELCNT     = D_SIZE;            /* element count              */
   g_dmaCTRLPKT1.ELDOFFSET = 4;                 /* element destination offset */
   g_dmaCTRLPKT1.ELSOFFSET = 0;                 /* element destination offset */
   g_dmaCTRLPKT1.FRDOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT1.FRSOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT1.PORTASGN  = PORTA_READ_PORTB_WRITE;
   g_dmaCTRLPKT1.RDSIZE    = ACCESS_16_BIT;     /* read size                  */
   g_dmaCTRLPKT1.WRSIZE    = ACCESS_16_BIT;     /* write size                 */
   g_dmaCTRLPKT1.TTYPE     = FRAME_TRANSFER ;   /* transfer type              */
   g_dmaCTRLPKT1.ADDMODERD = ADDR_INC1;         /* address mode read          */
   g_dmaCTRLPKT1.ADDMODEWR = ADDR_OFFSET;       /* address mode write         */
   g_dmaCTRLPKT1.AUTOINIT  = AUTOINIT_ON;       /* autoinit                   */

   g_dmaCTRLPKT2.SADD      = (uint32)&(mibspiRAM3->rx[0].data);    /* source address             */
   g_dmaCTRLPKT2.DADD      = (uint32)RXDATA3;    /* destination  address       */
   g_dmaCTRLPKT2.CHCTRL    = 0;                 /* channel control            */
   g_dmaCTRLPKT2.FRCNT     = 8;//1;                 /* frame count                */
   g_dmaCTRLPKT2.ELCNT     = D_SIZE;             /* element count              */
   g_dmaCTRLPKT2.ELDOFFSET = 0;                 /* element destination offset */
   g_dmaCTRLPKT2.ELSOFFSET = 4;                 /* element destination offset */
   g_dmaCTRLPKT2.FRDOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT2.FRSOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT2.PORTASGN  = PORTB_READ_PORTA_WRITE;
   g_dmaCTRLPKT2.RDSIZE    = ACCESS_16_BIT;     /* read size                  */
   g_dmaCTRLPKT2.WRSIZE    = ACCESS_16_BIT;     /* write size                 */
   g_dmaCTRLPKT2.TTYPE     = FRAME_TRANSFER ;   /* transfer type              */
   g_dmaCTRLPKT2.ADDMODERD = ADDR_OFFSET;         /* address mode read          */
   g_dmaCTRLPKT2.ADDMODEWR = ADDR_INC1;       /* address mode write         */
   g_dmaCTRLPKT2.AUTOINIT  = AUTOINIT_ON;       /* autoinit                   */

   /* upto 32 control packets are supported. */

   /* - setting dma control packets */
   dmaSetCtrlPacket(DMA_CH4,g_dmaCTRLPKT2);
   dmaSetCtrlPacket(DMA_CH5,g_dmaCTRLPKT1);

   dmaReqAssign(DMA_CH4, DMA_REQ14);
   dmaReqAssign(DMA_CH5, DMA_REQ15);

   /* - setting the dma channel to trigger on h/w request */
   dmaSetChEnable(DMA_CH4, DMA_HW);
   dmaSetChEnable(DMA_CH5, DMA_HW);

   /* - configuring dma control packets   */
   g_dmaCTRLPKT1.SADD      = (uint32)TXDATA4;    /* source address             */
   g_dmaCTRLPKT1.DADD      = (uint32)&(mibspiRAM4->tx[0].data);    /* destination  address       */
   g_dmaCTRLPKT1.CHCTRL    = 0;                 /* channel control            */
   g_dmaCTRLPKT1.FRCNT     = 8;//1;                 /* frame count                */
   g_dmaCTRLPKT1.ELCNT     = D_SIZE;            /* element count              */
   g_dmaCTRLPKT1.ELDOFFSET = 4;                 /* element destination offset */
   g_dmaCTRLPKT1.ELSOFFSET = 0;                 /* element destination offset */
   g_dmaCTRLPKT1.FRDOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT1.FRSOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT1.PORTASGN  = PORTA_READ_PORTB_WRITE;
   g_dmaCTRLPKT1.RDSIZE    = ACCESS_16_BIT;     /* read size                  */
   g_dmaCTRLPKT1.WRSIZE    = ACCESS_16_BIT;     /* write size                 */
   g_dmaCTRLPKT1.TTYPE     = FRAME_TRANSFER ;   /* transfer type              */
   g_dmaCTRLPKT1.ADDMODERD = ADDR_INC1;         /* address mode read          */
   g_dmaCTRLPKT1.ADDMODEWR = ADDR_OFFSET;       /* address mode write         */
   g_dmaCTRLPKT1.AUTOINIT  = AUTOINIT_ON;       /* autoinit                   */

   g_dmaCTRLPKT2.SADD      = (uint32)&(mibspiRAM4->rx[0].data);    /* source address             */
   g_dmaCTRLPKT2.DADD      = (uint32)RXDATA4;    /* destination  address       */
   g_dmaCTRLPKT2.CHCTRL    = 0;                 /* channel control            */
   g_dmaCTRLPKT2.FRCNT     = 8;//1;                 /* frame count                */
   g_dmaCTRLPKT2.ELCNT     = D_SIZE;             /* element count              */
   g_dmaCTRLPKT2.ELDOFFSET = 0;                 /* element destination offset */
   g_dmaCTRLPKT2.ELSOFFSET = 4;                 /* element destination offset */
   g_dmaCTRLPKT2.FRDOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT2.FRSOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT2.PORTASGN  = PORTB_READ_PORTA_WRITE;
   g_dmaCTRLPKT2.RDSIZE    = ACCESS_16_BIT;     /* read size                  */
   g_dmaCTRLPKT2.WRSIZE    = ACCESS_16_BIT;     /* write size                 */
   g_dmaCTRLPKT2.TTYPE     = FRAME_TRANSFER ;   /* transfer type              */
   g_dmaCTRLPKT2.ADDMODERD = ADDR_OFFSET;         /* address mode read          */
   g_dmaCTRLPKT2.ADDMODEWR = ADDR_INC1;       /* address mode write         */
   g_dmaCTRLPKT2.AUTOINIT  = AUTOINIT_ON;       /* autoinit                   */

   /* upto 32 control packets are supported. */

   /* - setting dma control packets */
   dmaSetCtrlPacket(DMA_CH6,g_dmaCTRLPKT2);
   dmaSetCtrlPacket(DMA_CH7,g_dmaCTRLPKT1);

   dmaReqAssign(DMA_CH6, DMA_REQ24);
   dmaReqAssign(DMA_CH7, DMA_REQ25);

   /* - setting the dma channel to trigger on h/w request */
   dmaSetChEnable(DMA_CH6, DMA_HW);
   dmaSetChEnable(DMA_CH7, DMA_HW);

   //dmaReqAssign(DMA_CH0, DMA_REQ0);
   //dmaReqAssign(DMA_CH1, DMA_REQ1);

   /* - configuring the mibspi dma , channel 0 , tx line -0 , rxline -1     */
   /* - refer to the device data sheet dma request source for mibspi tx/rx  */
   mibspiDmaConfig(mibspiREG1,0,0,1);
   mibspiDmaConfig(mibspiREG2,0,0,1);
   mibspiDmaConfig(mibspiREG3,0,0,1);
   mibspiDmaConfig(mibspiREG4,0,0,1);

   dmaEnable();

   /* - start the mibspi transfer tg 0 */
   mibspiTransfer(mibspiREG1,0 );
   mibspiTransfer(mibspiREG2,0 );
   mibspiTransfer(mibspiREG3,0 );
   mibspiTransfer(mibspiREG4,0 );

   while(1); /* loop forever */

/* USER CODE END */
}

/* USER CODE BEGIN (4) */
/** void mibspiEnableLoopback(mibspiBASE_t *mibspi )
*
*   enabling internal loopback on mibspix
*/
void mibspiEnableInternalLoopback(mibspiBASE_t *mibspi )
{
	/* enabling internal loopback */
    mibspi->GCR1 |= 1U << 16U;
}

/** void mibspiDmaConfig(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel)
*
*   configuring mibspi dma with
*
*       channel   > mibspi dma channel number
*       txchannel > transmit channel dedicated for mibspi
*       rxchannel > receive  channel dedicated for mibspi
*/
void mibspiDmaConfig(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel)
{
	uint32 bufid  = D_SIZE - 1;
	uint32 icount = 0;

    /* setting large count */
    mibspi->DMACNTLEN = 0x00000001;

    /*  setting initial count of DMA transfres */
    mibspi->DMACOUNT[channel] = BUFFER_SIZE << 16;

	/* setting transmit and receive channels */
	mibspi->DMACTRL[channel] |= (((rxchannel<<4)|txchannel) << 16);

	/* enabling transmit and receive dma */
	mibspi->DMACTRL[channel] |=  0x8000C000;

	/* setting Initial Count of DMA transfers and the buffer utilized for DMA transfer */
	mibspi->DMACTRL[channel] |=  (icount << 8) |(bufid<<24);

}


/** void loadDataPattern(uint32 psize, uint16* pptr)
*
*   loading a randam data chunk into system ram
*
*     pptr  > sys ram address
*     psize > chunkl size
*
*/
void loadDataPattern(uint32 psize, uint16* pptr)
{
	unsigned int i;

	for(i= 0; i < psize; i++)
	{
	    *pptr = i;
	    pptr++;
	}
 }
/* USER CODE END */

4 年多前

0 admin 4 年多前

TI__Guru**** 2539500 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好 Raheem、

您发布的代码对我来说看起来很好。您说 MibSPI1/2/3工作正常、但 MibSPI4不工作。

MibSPI4是否具有与 MibSPI1/2/3相同的组配置？

0 admin 4 年多前

TI__Guru**** 2539500 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好 QJ、

感谢您的回复。

对于测试，我注释了函数 mibspiTransfer (mibspiREG1，0)、 mibspiTransfer (mibspiREG2，0)和 mibspiTransfer (mibspiREG3，0)的调用。因此只调用了 mibspiTransfermibspiREG4,0)。对于具有25MHz SPICLOCK 的 mibSPI4、通过 DMA 进行的传输工作正常。 RXDATA4中接收到的数据符合预期。

对于第二个测试，我在函数 mibspiTransfer (mibspiREG1，0)、mibspiTransfer (mibspiREG2，0)、mibspiTransfer (mibspiREG3，0)和 mibspiTransfer (mibspiREG4，0)的调用中进行了注释，并将所有 mibSPI 的 SPIClock 设置为1MHz。一切都很好。正确接收所有 MibSPI 的所有数据并通过 DMA 传输回 RAM 位置。

在第三项测试中、我将所有 MibSPI 的 SPICLOCK 从1MHz 增加到4MHz、步长为1MHz。在2MHz 和3MHz 时、SPICLOCK 一切正常。 RAM 位置中的接收日期与预期的一样。但在4MHz 时、SPICLOCK RXDATA3和 RXDATA4的内容有一些不匹配。请参阅随附的 Code Composer Studio 调试视图屏幕截图。 RXDATA4的内容不是 TXDATA4中设置的升序内容。

0 admin 4 年多前

TI__Guru**** 2539500 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好 Raheem、

根据您的 DMA 封装配置和 DMA 通道分配、MibSPI4的 DMA 数据传输具有最低的优先级 MibSPI3。 MibSPI1 DMA 传输的优先级最高。

当 DMA 通道7 (MibSPI4 TX)将数据从 TXDATA4传输到 MibSPI4 TXRAM 时、如果有来自 MibSPI1/2/3 TX (DMA 通道1/3/5)的 DMA 传输请求、MibSPI4 DMA 传输将被仲裁、但 MibSPI4仍保持从 TX RAM 传输数据。

899、890、.904是前一个传输块的最后一个帧(帧#8)的数据。在 DMA 通道7传输"2"并仲裁之后、缓冲区#3中的现有数据"899"(缓冲区#0 = 0、缓冲区#1 = 1、缓冲区#2=2、缓冲区#3=899、缓冲区#4=890...)。

解决方案是使用 DMA 传输完成中断。

0 admin 4 年多前

TI__Guru**** 2539500 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好 QJ、

感谢您提出的解决方案建议。我扩展了代码、如下所示。 DMA 传输后 RAM 位置的接收日期看起来不错。遗憾的是、该解决方案涉及 CPU。是否有任何不涉及 CPU 的解决方案？在我们的 projectt 中、不允许中断。

(笑声)

  mibspiTransfer (mibspiREG1,0)；

  while (dmaGetInterruptStatus (DMA_CH0、BTC)=false)；

  mibspiTransfer (mibspiREG2.0)；

  while (dmaGetInterruptStatus (DMA_CH2、BTC)=false)；

  mibspiTransfer (mibspiREG3.0)；

  while (dmaGetInterruptStatus (DMA_CH4、BTC)=false)；

  mibspiTransfer (mibspiREG4,0)；

  while (dmaGetInterruptStatus (DMA_CH6、BTC)=false)；

(笑声)

0 admin 4 年多前

TI__Guru**** 2539500 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

是的、CPU 需要检查 BTC 标志。

基于 Arm 的微控制器（参考译文帖）

基于 Arm 的微控制器（参考译文帖）(Read Only)

[参考译文] TMS570LC4357：HAL 代码生成器 example_mibspiDMA 扩展到4个 mibSPI、每个都有1个传输组(mibSPI4在接收区域中有损坏的数据)