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器件型号：TMS320F2800157 工具/软件：
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我从事 RAM ECC 奇偶校验测试、 索引为1时、PIERAMParityTest 函数上有 ITRAP。
在第一次迭代之后、 "RPC 0x3FFD2C 返回程序计数器[Core]"会获取该值、该值不在 RAM 或闪存范围内。 从"STL_RAM_testRAMLogic"函数返回时、索引设置为1后、CPU 生成 ITRAP。 PIE_RAM_TEST_ADDR 上的数据为0x000BB155、原始数据为0x0009B157
我尝试了"sdl_ex_ram_ecc_parity_test"示例、它在同一个 MCU 上运行良好。
我已在函数中添加了"STL_RAM_"前缀。 这些函数与"sdl_ex_ram_ecc_parity_test"示例相同
// Using the I2CB interrupt (8.3) for testing here, but you may select others
#define STL_RAM_PIE_RAM_TEST_INT INT_I2CB
#define STL_RAM_PIE_RAM_TEST_PIEIFR_REG (PIECTRL_BASE + PIE_O_IFR8)
#define STL_RAM_PIE_RAM_TEST_PIEIFR_BIT (PIE_IFR8_INTX3)
#define STL_RAM_PIE_RAM_TEST_ACK INTERRUPT_ACK_GROUP8
#define STL_RAM_PIE_RAM_TEST_ADDR 0x00000DB4UL
uint16_t w_test_STA_TEST_RAM_ECC_PARITY(bool injectError)
{
(void)injectError;
uint16_t returnVal;
uint16_t failCount;
// Clear all the NMI and RAM error status flags.
MemCfg_clearCorrErrorStatus(MEMCFG_CERR_CPUREAD);
MemCfg_clearCorrErrorInterruptStatus(MEMCFG_UCERR_CPUREAD);
MemCfg_clearUncorrErrorStatus(MEMCFG_UCERR_CPUREAD);
SysCtl_clearAllNMIFlags();
SysCtl_clearInterruptStatus(0xFFFFFFFFU);
// Configure the correctable error interrupt threshold.
MemCfg_setCorrErrorThreshold(1U);
// Plug the NMI and RAM correctable error ISRs.
Interrupt_register(INT_NMI, &STL_RAM_nmiISR);
Interrupt_register(INT_SYS_ERR, &STL_RAM_corrErrorISR);
Interrupt_enable(INT_SYS_ERR);
SysCtl_setInterruptStatusMask(STL_RAM_MASK_ALL_BUT_RAM_ERR);
// Plug a routine to handle a PIE Vector Table parity error
EALLOW;
HWREG(CPUSYS_BASE + SYSCTL_O_PIEVERRADDR) = (uint32_t) &STL_RAM_pieVectErrorHandler;
EDIS;
// Enabling the NMI global interrupt (typically already enabled by boot ROM
// or GEL file).
SysCtl_enableNMIGlobalInterrupt();
// Enable RAM correctable error interrupt.
MemCfg_enableCorrErrorInterrupt(MEMCFG_CERR_CPUREAD);
// Enable Global Interrupt (INTM) and Real Time interrupt (DBGM).
EINT;
ERTM;
// Test parity functionality by injecting an error in parity RAM.
failCount = STL_RAM_runParityTest();
// Test parity functionality by injecting an error in PIE RAM.
failCount += STL_RAM_runPIERAMParityTest();
// Test ECC functionality by injecting a few correctable errors in m0Data_ECCParity.
failCount += STL_RAM_runCorrectableECCTest();
// Test ECC functionality by injecting an uncorrectable error in m0Data_ECCParity.
failCount += STL_RAM_runUncorrectableECCTest();
// Status of a successful handling of the RAM ECC/parity errors.
if(failCount != 0U)
{
//TEST FAIL: RAM ECC Parity Test!
returnVal = STA_TESTS_FAIL;
}
else
{
//TEST PASS: RAM ECC Parity Test!
returnVal = STA_TESTS_PASS;
}
return returnVal;
}
