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您好、您能帮助查找此设置的问题吗? 我已经用一根导线将 GPIO122 引脚接地、然后代码继续进入 ISR XINT1_ISR。
#include "F28x_Project.h" // Device Headerfile and Examples Include File
#include "easy2837xD_CPU1_sci_v8.5.h"
interrupt void xint1_isr(void);
void Xint1Setup(void);
void GpioIntSelect(void);
int main(void) {
DINT;
InitSysCtrl();
InitGpio();
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Would enable the pullup.
// Configure GPIO as Input for Interrupt
EALLOW;
GpioCtrlRegs.GPDMUX2.bit.GPIO122 = 0; // GPIO0 as GPIO
GpioCtrlRegs.GPDPUD.bit.GPIO122 = 1; // 1 = Disable pull-up on GPIO
GpioCtrlRegs.GPDDIR.bit.GPIO122 = 0; // Set as input
GpioCtrlRegs.GPDQSEL2.bit.GPIO122 = 0; // sync sampling
GpioCtrlRegs.GPDCTRL.bit.QUALPRD3 = 5; // require 5 SYSCLK samples high
InputXbarRegs.INPUT1SELECT = 0x122; // Route GPIO122 XINT1 via Input XBAR
EDIS;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
// Map external ISR
EALLOW;
PieVectTable.XINT1_INT = &xint1_isr;
EDIS;
PieCtrlRegs.PIEIER1.bit.INTx4 = 1; // XINT1 interrupt (PIE-1.4)
EALLOW;
XintRegs.XINT1CR.bit.ENABLE = 0; // ensure it’s off
XintRegs.XINT1CR.bit.POLARITY = 1; // Rising edge
XintRegs.XINT1CR.bit.ENABLE = 1; // Enable XINT1
EDIS;
IER |= M_INT1; // allow PIE Group 1 into the CPU
// Enable PIE interrupts
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
ledInitGpio();
pwmInit();
adcInit();
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
EALLOW;
GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // Set GPIO0 as output
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; // Set as GPIO
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up
EDIS;
// Step 6. IDLE loop. Just sit and loop forever (optional):
while(1)
{
backgroundWork();
}
}
//------------------------------------------------------------------
float TestVal = 0;
interrupt void xint1_isr(void)
{
// Clear interrupt flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
TestVal = 1;
// Re-enable XINT1 so it can fire again
// (this also clears its internal pending flag)
XintRegs.XINT1CR.bit.ENABLE = 0;
XintRegs.XINT1CR.bit.ENABLE = 1;
}
PWM 配置的代码如下:
DINT;
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks
EDIS;
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.EPWM1_INT = &epwm1_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
EPwm1Regs.ETSEL.bit.INTSELCMP = 1; // Use ePWM1 Compare C for triggering event
EPwm1Regs.CMPC = 0;
EPwm1Regs.CMPD = 0;
EPwm1Regs.ETSEL.bit.INTSEL = 1; // select when interrupt start
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced
EDIS;
IER |= M_INT3;
EPwm1Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
ADC 配置的代码如下:
//Map ISR functions
EALLOW;
PieVectTable.ADCA1_INT = &adca1_isr; //function for ADCA interrupt 1
EDIS;
//Configure the ADC and power it up
// ConfigureADC();
EALLOW;
//write configurations
// max ADC clock freq is 50MHz
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdcbRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_16BIT, ADC_SIGNALMODE_DIFFERENTIAL);
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
// start the interrupt at the end of SOC (late interrput mode)
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//power up the ADC
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
//delay for 1ms to allow ADC time to power up
DELAY_US(1000);
EDIS;
EALLOW;
// Assumes ePWM clock is already enabled
EPwm1Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA
EPwm1Regs.ETSEL.bit.SOCASELCMP = 1; // compare on C or D
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // 4 = COMPC incrementing
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EDIS;
Uint16 acqps;
acqps = 63; //320ns
//Select the channels to convert and end of conversion flag
EALLOW;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 //iU
AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //trigger on ePWM1 SOCA/C
AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 1; // SOC0 is high priority
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 2; //SOC1 will convert pin 2 //iV
AdcaRegs.ADCSOC1CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 5;
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 4; //iW
AdcaRegs.ADCSOC2CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 5;
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
EDIS;
acqps = 14; //75ns
EALLOW;
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 4; // Vab
AdcbRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //trigger on ePWM1 SOCA/C
AdcbRegs.ADCSOC1CTL.bit.CHSEL = 5; //Vbc
AdcbRegs.ADCSOC1CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 5; //trigger on ePWM1 SOCA/C
AdcbRegs.ADCSOC2CTL.bit.CHSEL = 3; //Vdc
AdcbRegs.ADCSOC2CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC2CTL.bit.TRIGSEL = 5; //trigger on ePWM1 SOCA/C
AdcbRegs.ADCSOC3CTL.bit.CHSEL = 2; //Idc
AdcbRegs.ADCSOC3CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC3CTL.bit.TRIGSEL = 5; //trigger on ePWM1 SOCA/C
EDIS;
//Enable global Interrupts and higher priority real-time debug events:
IER |= M_INT1; //Enable group 1 interrupts
//enable PIE interrupt
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
//sync ePWM
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;