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部件号:TMS320F28379D主题: ADS1258 中讨论的其他器件
工具/软件:
您好:
我之前创建了一个线程、但对它的响应很少、因此我在这里创建了一个新线程。 我使用的是 TMS320F28379D 控制器、我通过 SPI 通信与 ADS1258 连接。 我的主要任务是读取 ADS1258 的默认 CONFIG0 寄存器、其默认值为 0x0A。
1) 在读取默认寄存器时、我是否需要将 PWDN 和 RESET 引脚设为高电平、或者是否可以直接运行默认寄存器读取代码?
2) ADS1258 在模式 00 (CPOL = 0、CPHA = 0) 下使用 SPI 进行通信、因此在 TMS320F28379D 设置中、我设置了 CLKPOLARITY = 0 和 CLK_PHASE = 0。
3) 我将数据 0x40、0x00 发送到 ADS1258。 我还附上了一个波形。 请进行验证。我发送了连续数据、只是为了使波形可见、因为我无法在单次模式下捕获。

4) 我已将通信频率设置为 1MHz、并附上了代码。
请仔细查看我的代码、并准确告诉我可能出错的地方。 我已经尝试读取默认寄存器将近一个月了、因此我确实需要帮助。
#include "F28x_Project.h"
#include "ADS1258.h"
static uint8_t registerMap[NUM_REGISTERS];
uint8_t DataTx[2] = { 0 };
uint8_t DataRx[2] = { 0 };
void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file InitSysCtrl();
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// Setup only the GPIO only for SPI-A functionality
// This function is found in F2837xD_Spi.c
InitSpiaGpio();
InitADS1258Gpio();
// Step 3. Clear all interrupts:
DINT;
//
// Initialize PIE control registers to their default state.
// The default state is all PIE __interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.\
InitPieCtrl();
// Disable CPU __interrupts and clear all CPU __interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the __interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
InitPieVectTable();
// Step 4. Initialize the Device Peripherals:
spi_fifo_init(); // Initialize the SPI FIFO
// Step 5. User specific code:
adcStartupRoutine();
for(;;)
{
}
}
void adcStartupRoutine(void)
{
/* (OPTIONAL) Provide additional delay time for power supply settling */
DELAY_US(50000);
GpioDataRegs.GPBSET.bit.GPIO61 = 1; // CS HIGH
/* (REQUIRED) Set nRESET/nPWDN pin high for ADC operation */
GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1; // PWDN low
DELAY_US(100);
GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1; // PWDN high
DELAY_US(10000);
/* (REQUIRED) tWAKE delay */
DELAY_US(5000);
readSingleRegister(0X00);
}
uint8_t spiSendReceiveByte(uint8_t data)
{
// Wait if TX buffer is full
while (SpiaRegs.SPISTS.bit.BUFFULL_FLAG);
// Send data (upper byte only transmitted)
SpiaRegs.SPITXBUF = ((uint16_t)data << 8);
}
void spiSendReceiveArrays(uint8_t DataTx[], uint8_t DataRx[], uint8_t byteLength)
{
volatile uint16_t dummy;
/* Set the nCS pin LOW */
GpioDataRegs.GPBCLEAR.bit.GPIO61 = 1; // CS LOW
uint8_t i;
for (i = 0; i < byteLength; i++)
{
spiSendReceiveByte(DataTx[i]);
}
spiSendReceiveByte(0x00);
if (SpiaRegs.SPISTS.bit.BUFFULL_FLAG == 1)
{
DataRx[0] =(SpiaRegs.SPIRXBUF >> 8);
}
spiSendReceiveByte(0x00);
if (SpiaRegs.SPISTS.bit.BUFFULL_FLAG == 1)
{
DataRx[1] =(SpiaRegs.SPIRXBUF >> 8);
}
GpioDataRegs.GPBSET.bit.GPIO61 = 1; // CS HIGH
}
void spi_fifo_init()
{
//
// Initialize SPI FIFO registers
//
SpiaRegs.SPIFFTX.all = 0xE040;
SpiaRegs.SPIFFRX.all = 0x2044;
SpiaRegs.SPIFFCT.all = 0x0;
//
// Initialize core SPI registers
//
InitSpi();
}
void InitADS1258Gpio(void)
{
EALLOW;
GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 0; // GPIO80 as GPIO
GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1; // Output (PWDN)
GpioCtrlRegs.GPDMUX1.bit.GPIO97 = 0; // GPIO84 as GPIO
GpioCtrlRegs.GPDDIR.bit.GPIO97 = 1; // Output (RESET)
GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 0; // GPIO4 as GPIO
GpioCtrlRegs.GPCDIR.bit.GPIO67 = 1; // Output (START)
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0; // GPIO4 as GPIO
GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1; // Output (CS)
EDIS;
}
uint8_t readSingleRegister(uint8_t address)
{
/* Build TX array and send it */
DataTx[0] = OPCODE_RREG | (address & OPCODE_A_MASK);
spiSendReceiveArrays(DataTx, DataRx, 2);
/* Update register array and return read result*/
registerMap[address] = DataRx[1];
return DataRx[1];
}
void InitSpi(void)
{
// Initialize SPI-A
// Set reset low before configuration changes
// Clock polarity (0 == rising, 1 == falling)
// 16-bit character
// Enable loop-back
SpiaRegs.SPICCR.bit.SPISWRESET = 0;
SpiaRegs.SPIPRI.bit.TRIWIRE = 1;
SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
SpiaRegs.SPICCR.bit.SPICHAR = 7;
SpiaRegs.SPICCR.bit.SPILBK = 0;
// Enable master (0 == slave, 1 == master)
// Enable transmission (Talk)
// Clock phase (0 == normal, 1 == delayed)
// SPI interrupts are disabled
SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
SpiaRegs.SPICTL.bit.TALK = 1;
SpiaRegs.SPICTL.bit.CLK_PHASE = 0;
SpiaRegs.SPICTL.bit.SPIINTENA = 0;
// Set the baud rate
SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 24;
// Set FREE bit
// Halting on a breakpoint will not halt the SPI
SpiaRegs.SPIPRI.bit.FREE = 1;
// Release the SPI from reset
SpiaRegs.SPICCR.bit.SPISWRESET = 1;
}
void InitSpiGpio()
{
InitSpiaGpio();
}
//
// InitSpiaGpio - Initialize SPIA GPIOs
//
void InitSpiaGpio()
{
EALLOW;
//
// Enable internal pull-up for the selected pins
//
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
//
GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO16 (SPISIMOA)
GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; // Enable pull-up on GPIO17 (SPISOMIA)
GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0; // Enable pull-up on GPIO18 (SPICLKA)
GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pull-up on GPIO19 (SPISTEA)
//
// Set qualification for selected pins to asynch only
//
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.
//
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO16 (SPISIMOA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO17 (SPISOMIA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO18 (SPICLKA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO19 (SPISTEA)
GpioCtrlRegs.GPBGMUX2.bit.GPIO58 = 3; // Configure GPIO16 as SPISIMOA
GpioCtrlRegs.GPBGMUX2.bit.GPIO59 = 3; // Configure GPIO17 as SPISOMIA
GpioCtrlRegs.GPBGMUX2.bit.GPIO60 = 3; // Configure GPIO18 as SPICLKA
GpioCtrlRegs.GPBGMUX2.bit.GPIO61 = 3; // Configure GPIO19 as SPISTEA
//
//Configure SPI-A pins using GPIO regs
//
// This specifies which of the possible GPIO pins will be SPI functional
// pins.
// Comment out other unwanted lines.
//
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // Configure GPIO16 as SPISIMOA
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // Configure GPIO17 as SPISOMIA
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // Configure GPIO18 as SPICLKA
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // Configure GPIO19 as SPISTEA
EDIS;
}