[参考译文] TMS320F28388D：是否有可能获得虚假断言？ ，调试器显示错误的代码行

您好，

我们使用“断言”来确保条件正确，然后再继续操作。

断言(sysctl_getLowSpeedClock(device_OSCSRC_FREQ)== device_LSPCLK_FREQ)；

如果您的代码陷入此断言，则表示 LSP 时钟未在  device_LSPCLK_FREQ 中配置。 如果您在 device.h 文件中更改了 LSPCLK 分隔符，请确保 DEVICE_LSPCLK_FREQ 也相应更新。 否则 ，时钟设置存在一些差异。

断言(SPI_ISBaseValid(BAS))；

您能否深入了解代码并确保基本变量值有效？ 从您的代码中，似乎只能选择有效的地址。 请确认以确保没有初始化问题。

[引用 userid="508064" url="~ë/support/emcp-omers-group/CC2000 /f/c2000-微控制器-forum/1071727/tms320f28388d-is-possible to -get - sample-debuger-se-souts - pice-wrong - pic 代码行"]此外，我的调试器在调试过程中显示错误的代码[如下面的代码]

您是否使用了错误的 SPI.c 文件进行调试？ CCS 项目版本中是否有 SPI.c，或者您使用的是 driverlib.lib？ 请确认您正在从正确的设备文件夹中选取 SPI.c/driverlib.lib。

此致，

维纳

你好，维纳！

感谢您的回答。

[引用 userid="128297" url="~/support/icontrs/c2000微控制器-组/CC2000 /f/c2000 -微控制器-论坛/1071727/tms320f28388d-it-possible to get - sample-der-debuger-se-souts - code-line/3965705#3965705""可以确定变量的有效范围，并确保该变量的内部值有效。] 从您的代码中，似乎只能选择有效的地址。 请确认以确保没有初始化问题。

是的。我做了一次，基本地址以某种方式递增了一个。例如从0x6100到0x6101。 我希望这是我的错误。  

[引用 userid="128297" url="~/support/moncs/c2000-monics)-组/CC2000 /f/c2000 -微控制器-论坛/1071727/tms320f28388d-ice-possible -获取-虚假-断言-调试器-显示错误-代码行/3965705#3965705"请确认您从设备中选取了正确的 SPI/driverlib[报价]。

事实上，我只是在使用 TI Ware 中的示例。 我没有接触到任何图书馆。 我对 CCS 没有太多的经验，但我看到的是，在示例中，驱动程序库只有头文件，而不是 SPI.c。  而是驱动程序 lib.lib。

您知道如何删除 driverlib.lib 并使用 driverlib？

谢谢，

您好，

您只需从 CCS 项目中删除.lib 文件并添加所需的 driverlib 源代码。

此致，

维纳

你好，维纳！

感谢您的回答，但结果不起作用。

我删除了 lib，并且源代码已经被删除，但我遇到了许多错误，如 错误#10234-D：未解析的符号仍然存在

你好，维纳！

现在我得到了这种说法。

  断言(sysctl_getLowSpeedClock(device_OSCSRC_FREQ)== device_LSPCLK_FREQ)；

我只是想以如此25MHz 的高速使用 SPI，但我总是会遇到资产错误。 ：s

是否也可以使用 sysconfig 设置时钟？

谢谢，

你好，维纳！

现在我收到了此 Asser 错误：s  

断言(sysctl_getLowSpeedClock(device_OSCSRC_FREQ)== device_LSPCLK_FREQ)；

我尝试在如此25MHz 的高速下使用 SPI，但我在任何地方都遇到 Asser 错误。

是否也可以对 sysconfig 进行时钟设置？

谢谢，

[引用 userid="508064" url="~ë/support/icons/c2000-icro-group/c2f/c2000-微控制器-forum/1071727/tms320f28388d-ice-poss-it-d- sugger-sout-exfile-wrong-code-line/3970729#3970729"]

我尝试在如此25MHz 的高速下使用 SPI，但我在任何地方都遇到 Asser 错误。

[/引用]

您能否共享您正在使用的 device.h 和 device.c 文件？ 您是否已更改了 LSP 时钟分配器的默认设置？

[引用 userid="508064" url="~ë/support/icons/c2000-icro-group/c2f/c2000-微控制器-forum/1071727/tms320f28388d-ice-poss-it-d- sugger-sout-exfile-wrong-code-line/3970729#3970729"]

我尝试在如此25MHz 的高速下使用 SPI，但我在任何地方都遇到 Asser 错误。

[/引用]

您是否使用 SPI_enableHighSpeedMode()来启用高速模式？ 断言是否在该函数内导致问题？

此致，

维纳

你好，维纳！

[引用 userid="128297" url="~/support/icros/c2000-icro-group/c2f/c2000-icro-forum-forum/1071727/tms320f28388d-ice-possible to get－spurious－der-debugger-secture-se-outse-wrong－code-line/3971409#3971409]]]

您能否共享您正在使用的 device.h 和 device.c 文件？ 您是否已更改了 LSP 时钟分配器的默认设置？

[/引用]

 是的，我更改为在高速模式下运行 SPI。  

这是我的初始化代码 device.h 和 device.c

    SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_1);

    SPI_setConfig(SPIA_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA0,
                  SPI_MODE_MASTER, 20000000, 16);
    SPI_enableHighSpeedMode(SPIA_BASE);

//#############################################################################
//
// FILE:   device.h
//
// TITLE:  Device setup for examples.
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.co/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################

//
// Included Files
//

#include "driverlib.h"

#if (!defined(CPU1) && !defined(CPU2))
#error "You must define CPU1 or CPU2 in your project properties.  Otherwise, \
the offsets in your header files will be inaccurate."
#endif

#if (defined(CPU1) && defined(CPU2))
#error "You have defined both CPU1 and CPU2 in your project properties.  Only \
a single CPU should be defined."
#endif
//*****************************************************************************
//
// Defines for pin numbers and other GPIO configuration
//
//*****************************************************************************
//
// LEDs
//
#define DEVICE_GPIO_PIN_LED1        31U   // GPIO number for LD1
#define DEVICE_GPIO_PIN_LED2        34U   // GPIO number for LD2
#define DEVICE_GPIO_PIN_LED3        145U  // GPIO number for LD7 (EtherCAT Error LED)
#define DEVICE_GPIO_PIN_LED4        146U  // GPIO number for LD8 (EtherCAT Run LED)
#define DEVICE_GPIO_CFG_LED1        GPIO_31_GPIO31    // "pinConfig" for LD1
#define DEVICE_GPIO_CFG_LED2        GPIO_34_GPIO34    // "pinConfig" for LD2
#define DEVICE_GPIO_CFG_LED3        GPIO_145_GPIO145  // "pinConfig" for LD7
#define DEVICE_GPIO_CFG_LED4        GPIO_146_GPIO146  // "pinConfig" for LD8


//
// SCI for USB-to-UART adapter on FTDI chip
//
#define DEVICE_GPIO_PIN_SCIRXDA     28U             // GPIO number for SCI RX
#define DEVICE_GPIO_PIN_SCITXDA     29U             // GPIO number for SCI TX
#define DEVICE_GPIO_CFG_SCIRXDA     GPIO_28_SCIA_RX // "pinConfig" for SCI RX
#define DEVICE_GPIO_CFG_SCITXDA     GPIO_29_SCIA_TX // "pinConfig" for SCI TX

//
// CANA
//
#define DEVICE_GPIO_PIN_CANTXA      37U  // GPIO number for CANTXA
#define DEVICE_GPIO_PIN_CANRXA      36U  // GPIO number for CANRXA

//
// CAN External Loopback
//
#define DEVICE_GPIO_CFG_CANRXA      GPIO_36_CANA_RX  // "pinConfig" for CANA RX
#define DEVICE_GPIO_CFG_CANTXA      GPIO_37_CANA_TX  // "pinConfig" for CANA TX
#define DEVICE_GPIO_CFG_CANRXB      GPIO_10_CANB_RX  // "pinConfig" for CANB RX
#define DEVICE_GPIO_CFG_CANTXB      GPIO_12_CANB_TX  // "pinConfig" for CANB TX

//
// MCAN
//
#define DEVICE_GPIO_CFG_MCANRXA    GPIO_30_MCAN_RX  // "pinConfig" for MCAN RX
#define DEVICE_GPIO_CFG_MCANTXA    GPIO_31_MCAN_TX  // "pinConfig" for MCAN TX

//
// FSI
//
#define DEVICE_GPIO_PIN_FSI_RXCLKA      9U  // GPIO number for FSI RXCLKA
#define DEVICE_GPIO_PIN_FSI_RX0A        8U  // GPIO number for FSI RX0A
#define DEVICE_GPIO_PIN_FSI_RX1A        10U  // GPIO number for FSI RX1A

#define DEVICE_GPIO_PIN_FSI_RXCLKB      60U  // GPIO number for FSI RXCLKB
#define DEVICE_GPIO_PIN_FSI_RX0B        58U  // GPIO number for FSI RX0B
#define DEVICE_GPIO_PIN_FSI_RX1B        59U  // GPIO number for FSI RX1B

#define DEVICE_GPIO_PIN_FSI_RXCLKC      14U  // GPIO number for FSI RXCLKC
#define DEVICE_GPIO_PIN_FSI_RX0C        12U  // GPIO number for FSI RX0C
#define DEVICE_GPIO_PIN_FSI_RX1C        13U  // GPIO number for FSI RX1C


#define DEVICE_GPIO_CFG_FSI_TXCLK       GPIO_27_FSITXA_CLK  // "pinConfig" for FSI TXCLK
#define DEVICE_GPIO_CFG_FSI_TX0         GPIO_26_FSITXA_D0   // "pinConfig" for FSI TX0
#define DEVICE_GPIO_CFG_FSI_TX1         GPIO_25_FSITXA_D1   // "pinConfig" for FSI TX1

#define DEVICE_GPIO_CFG_FSI_RXCLKA      GPIO_9_FSIRXA_CLK   // "pinConfig" for FSI RXCLKA
#define DEVICE_GPIO_CFG_FSI_RX0A        GPIO_8_FSIRXA_D0    // "pinConfig" for FSI RX0A
#define DEVICE_GPIO_CFG_FSI_RX1A        GPIO_10_FSIRXA_D1   // "pinConfig" for FSI RX1A

#define DEVICE_GPIO_CFG_FSI_RXCLKB      GPIO_60_FSIRXB_CLK  // "pinConfig" for FSI RXCLKB
#define DEVICE_GPIO_CFG_FSI_RX0B        GPIO_58_FSIRXB_D0   // "pinConfig" for FSI RX0B
#define DEVICE_GPIO_CFG_FSI_RX1B        GPIO_59_FSIRXB_D1   // "pinConfig" for FSI RX1B

#define DEVICE_GPIO_CFG_FSI_RXCLKC      GPIO_14_FSIRXC_CLK  // "pinConfig" for FSI RXCLKC
#define DEVICE_GPIO_CFG_FSI_RX0C        GPIO_12_FSIRXC_D0   // "pinConfig" for FSI RX0C
#define DEVICE_GPIO_CFG_FSI_RX1C        GPIO_13_FSIRXC_D1   // "pinConfig" for FSI RX1C

//!  --------------------------------
//!    Signal   |  I2CA   |  I2CB
//!  --------------------------------
//!     SCL     | GPIO105 |  GPIO41
//!     SDA     | GPIO104 |  GPIO40
//!  --------------------------------
//I2CA GPIO pins
#define DEVICE_GPIO_PIN_SDAA    104
#define DEVICE_GPIO_PIN_SCLA    105

//I2CB GPIO pins
#define DEVICE_GPIO_PIN_SDAB    40
#define DEVICE_GPIO_PIN_SCLB    41

#define DEVICE_GPIO_CFG_SDAA GPIO_104_I2CA_SDA
#define DEVICE_GPIO_CFG_SCLA GPIO_105_I2CA_SCL

#define DEVICE_GPIO_CFG_SDAB GPIO_40_I2CB_SDA
#define DEVICE_GPIO_CFG_SCLB GPIO_41_I2CB_SCL


//*****************************************************************************
//
// Defines related to clock configuration
//
//*****************************************************************************
#ifdef USE_20MHZ_XTAL

//
// 20MHz XTAL on controlCARD. For use with SysCtl_getClock() and
// SysCtl_getAuxClock().
//
#define DEVICE_OSCSRC_FREQ          20000000U

//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// PLLSYSCLK = 20MHz (XTAL_OSC) * 40 (IMULT) / (2 (REFDIV) * 2 (ODIV) * 1(SYSDIV))
//
#define DEVICE_SETCLOCK_CFG          (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) | \
                                      SYSCTL_REFDIV(2) | SYSCTL_ODIV(2) | \
                                      SYSCTL_SYSDIV(1) | SYSCTL_PLL_ENABLE | \
                                      SYSCTL_DCC_BASE_1)

//
// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
// code below if a different clock configuration is used!
//
#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 40) / (2 * 2 * 1))

//
// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default
// low speed peripheral clock divider of 4. Update the code below if a
// different LSPCLK divider is used!
//
#define DEVICE_LSPCLK_FREQ          (DEVICE_SYSCLK_FREQ / 4)

//
// Define to pass to SysCtl_setAuxClock(). Will configure the clock as follows:
// AUXPLLCLK = 20MHz (XTAL_OSC) * 50 (IMULT) / (2 (REFDIV) * 4 (ODIV) * 1(AUXPLLDIV) )
//
#define DEVICE_AUXSETCLOCK_CFG       (SYSCTL_AUXPLL_OSCSRC_XTAL | SYSCTL_AUXPLL_IMULT(50) |  \
                                      SYSCTL_REFDIV(2U) | SYSCTL_ODIV(4U) | \
                                      SYSCTL_AUXPLL_DIV_1 | SYSCTL_AUXPLL_ENABLE | \
                                      SYSCTL_DCC_BASE_0)

//
// 125MHz AUXCLK frequency based on the above DEVICE_AUXSETCLOCK_CFG. Update
// the code below if a different clock configuration is used!
//
#define DEVICE_AUXCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 50) / (2 * 4 * 1))


#else // USE_25MHZ_XTAL

//
// 25MHz XTAL on controlCARD. For use with SysCtl_getClock() and
// SysCtl_getAuxClock().
//
#define DEVICE_OSCSRC_FREQ          25000000U

//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// PLLSYSCLK = 25MHz (XTAL_OSC) * 32 (IMULT) / (2 (REFDIV) * 2 (ODIV) * 1(SYSDIV))
//
#define DEVICE_SETCLOCK_CFG          (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(32) | \
                                      SYSCTL_REFDIV(2) | SYSCTL_ODIV(2) | \
                                      SYSCTL_SYSDIV(1) | SYSCTL_PLL_ENABLE | \
                                      SYSCTL_DCC_BASE_1)

//
// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
// code below if a different clock configuration is used!
//
#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 32) / (2 * 2 * 1))

//
// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default
// low speed peripheral clock divider of 4. Update the code below if a
// different LSPCLK divider is used!
//
#define DEVICE_LSPCLK_FREQ          (DEVICE_SYSCLK_FREQ / 1)

//
// Define to pass to SysCtl_setAuxClock(). Will configure the clock as follows:
// AUXPLLCLK = 25MHz (XTAL_OSC) * 40 (IMULT) / (2 (REFDIV) * 4 (ODIV) * 1(AUXPLLDIV) )
//
#define DEVICE_AUXSETCLOCK_CFG       (SYSCTL_AUXPLL_OSCSRC_XTAL | SYSCTL_AUXPLL_IMULT(40) |  \
                                      SYSCTL_REFDIV(2U) | SYSCTL_ODIV(4U) | \
                                      SYSCTL_AUXPLL_DIV_1 | SYSCTL_AUXPLL_ENABLE | \
                                      SYSCTL_DCC_BASE_0)

//
// 125MHz AUXCLK frequency based on the above DEVICE_AUXSETCLOCK_CFG. Update
// the code below if a different clock configuration is used!
//
#define DEVICE_AUXCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 40) / (2 * 4 * 1))

#endif

//*****************************************************************************
//
// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro
// will convert the desired delay in microseconds to the count value expected
// by the function. \b x is the number of microseconds to delay.
//
//*****************************************************************************
#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L /  \
                              (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L)

//
//  Defines for setting FSI clock speeds
//
#define FSI_PRESCALE_50MHZ          2U
#define FSI_PRESCALE_25MHZ          4U
#define FSI_PRESCALE_10MHZ          10U
#define FSI_PRESCALE_5MHZ           20U
							  
//*****************************************************************************
//
// Macros related to booting CPU2 and CM. These can be used while invoking the
// functions Device_bootCPU2() and Device_bootCM(). 
//
// Note that the macros CM_BOOT_FREQ_125MHZ and CPU2_BOOT_FREQ_200MHZ are used
// in the functions Device_bootCM() and Device_bootCPU2() respectively. Please
// update the function and the macros if you are using a different clock
// frequency.
//
//*****************************************************************************
#ifdef CPU1
#define BOOT_KEY                                0x5A000000UL
#define CM_BOOT_FREQ_125MHZ                     0x7D00U
#define CPU2_BOOT_FREQ_200MHZ                   0xC800U

#define BOOTMODE_BOOT_TO_FLASH_SECTOR0          0x03U
#define BOOTMODE_BOOT_TO_FLASH_SECTOR4          0x23U
#define BOOTMODE_BOOT_TO_FLASH_SECTOR8          0x43U
#define BOOTMODE_BOOT_TO_FLASH_SECTOR13         0x63U
#define BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR0   0x0AU
#define BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR4   0x2AU
#define BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR8   0x4AU
#define BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR13  0x6AU
#define BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM  0x0CU
#define BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_S0RAM  0x0CU
#define BOOTMODE_BOOT_TO_M0RAM                  0x05U
#define BOOTMODE_BOOT_TO_S0RAM                  0x05U
#define BOOTMODE_BOOT_TO_USEROTP                0x0BU

#define BOOTMODE_IPC_MSGRAM_COPY_LENGTH_100W    0x10000U
#define BOOTMODE_IPC_MSGRAM_COPY_LENGTH_200W    0x20000U
#define BOOTMODE_IPC_MSGRAM_COPY_LENGTH_300W    0x30000U
#define BOOTMODE_IPC_MSGRAM_COPY_LENGTH_400W    0x40000U
#define BOOTMODE_IPC_MSGRAM_COPY_LENGTH_500W    0x50000U
#define BOOTMODE_IPC_MSGRAM_COPY_LENGTH_600W    0x60000U
#define BOOTMODE_IPC_MSGRAM_COPY_LENGTH_700W    0x70000U
#define BOOTMODE_IPC_MSGRAM_COPY_LENGTH_800W    0x80000U
#define BOOTMODE_IPC_MSGRAM_COPY_LENGTH_900W    0x90000U
#define BOOTMODE_IPC_MSGRAM_COPY_LENGTH_1000W   0xA0000U
#endif

//*****************************************************************************
//
// Defines, Globals, and Header Includes related to Flash Support
//
//*****************************************************************************
#ifdef _FLASH
#include <stddef.h>

extern uint16_t RamfuncsLoadStart;
extern uint16_t RamfuncsLoadEnd;
extern uint16_t RamfuncsLoadSize;
extern uint16_t RamfuncsRunStart;
extern uint16_t RamfuncsRunEnd;
extern uint16_t RamfuncsRunSize;

#define DEVICE_FLASH_WAITSTATES 3

#endif

//*****************************************************************************
//
// Function Prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup device_api
//! @{
//
//*****************************************************************************

//*****************************************************************************
//
//! @brief Function to initialize the device. Primarily initializes system control to a
//! known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
//! and enabling the clocks to the peripherals.
//!
//! \param None.
//! \return None.
//
//*****************************************************************************
extern void Device_init(void);

#ifdef CPU1

//*****************************************************************************
//
//! @brief Function to boot CPU2.
//!
//! \param bootmode is the mode in which CPU2 should boot.
//!
//! Available bootmodes :
//!      - BOOTMODE_BOOT_TO_FLASH_SECTOR0
//!      - BOOTMODE_BOOT_TO_FLASH_SECTOR4
//!      - BOOTMODE_BOOT_TO_FLASH_SECTOR8
//!      - BOOTMODE_BOOT_TO_FLASH_SECTOR13
//!      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR0
//!      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR4
//!      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR8
//!      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR13
//!      - BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM
//!      - BOOTMODE_BOOT_TO_M0RAM
//!      - BOOTMODE_BOOT_TO_USEROTP
//!
//! Note that while using BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM,
//! BOOTMODE_IPC_MSGRAM_COPY_LENGTH_xxxW must be ORed with the bootmode parameter
//!
//! This function must be called after Device_init function
//! \return None.
//
//*****************************************************************************
extern void Device_bootCPU2(uint32_t bootmode);

//*****************************************************************************
//
//! @brief Function to boot CM
//!
//! \param bootmode is the mode in which CM should boot.
//!
//! Available bootmodes :
//!      - BOOTMODE_BOOT_TO_FLASH_SECTOR0
//!      - BOOTMODE_BOOT_TO_FLASH_SECTOR4
//!      - BOOTMODE_BOOT_TO_FLASH_SECTOR8
//!      - BOOTMODE_BOOT_TO_FLASH_SECTOR13
//!      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR0
//!      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR4
//!      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR8
//!      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR13
//!      - BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_S0RAM
//!      - BOOTMODE_BOOT_TO_S0RAM
//!      - BOOTMODE_BOOT_TO_USEROTP
//!
//! Note that while using BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM,
//! BOOTMODE_IPC_MSGRAM_COPY_LENGTH_xxxW must be ORed with the bootmode parameter
//!
//! This function must be called after Device_init function
//! \return None.
//
//*****************************************************************************
extern void Device_bootCM(uint32_t bootmode);

//*****************************************************************************
//
//!
//! @brief Function to verify the XTAL frequency
//! \param freq is the XTAL frequency in MHz
//! \return The function return true if the the actual XTAL frequency matches with the
//! input value
//
//*****************************************************************************
extern bool Device_verifyXTAL(float freq);
#endif

//*****************************************************************************
//!
//!
//! @brief Function to turn on all peripherals, enabling reads and writes to the
//! peripherals' registers.
//!
//! Note that to reduce power, unused peripherals should be disabled.
//!
//! @param None
//! @return None
//
//*****************************************************************************
extern void Device_enableAllPeripherals(void);
//*****************************************************************************
//!
//!
//! @brief Function to disable pin locks on GPIOs.
//!
//! @param None
//! @return None
//
//*****************************************************************************
extern void Device_initGPIO(void);
//*****************************************************************************
//!
//! @brief Function to enable pullups for the unbonded GPIOs on the 176PTP package:
//! GPIOs     Grp Bits
//! 95-132    C   31
//!           D   31:0
//!           E   4:0
//! 134-168   E   31:6
//!           F   8:0
//!
//! @param None
//! @return None
//
//*****************************************************************************
extern void Device_enableUnbondedGPIOPullupsFor176Pin(void);
//*****************************************************************************
//!
//! @brief Function to enable pullups for the unbonded GPIOs on the
//! 176PTP package.
//!
//! @param None
//! @return None
//
//*****************************************************************************

extern void Device_enableUnbondedGPIOPullups(void);
//*****************************************************************************
//!
//! @brief Error handling function to be called when an ASSERT is violated
//!
//! @param *filename File name in which the error has occurred
//! @param line Line number within the file
//! @return None
//
//*****************************************************************************

extern void __error__(char *filename, uint32_t line);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//#############################################################################
//
// FILE:   device.c
//
// TITLE:  Device setup for examples.
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.co/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################

//
// Included Files
//
#include "device.h"

//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
//
//*****************************************************************************
void Device_init(void)
{
    //
    // Disable the watchdog
    //
    SysCtl_disableWatchdog();

#ifdef _FLASH
    //
    // Copy time critical code and flash setup code to RAM. This includes the
    // following functions: InitFlash();
    //
    // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
    // are created by the linker. Refer to the device .cmd file.
    //
    memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);

    //
    // Call Flash Initialization to setup flash waitstates. This function must
    // reside in RAM.
    //
    Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
#endif

#ifdef CPU1
    //
    // Verify the crystal frequency.
    // Note: This check can be removed if you are not using XTAL as the PLL
    // source
    //
    if( ((DEVICE_SETCLOCK_CFG & SYSCTL_OSCSRC_M) == SYSCTL_OSCSRC_XTAL) ||
        ((DEVICE_SETCLOCK_CFG & SYSCTL_OSCSRC_M) == SYSCTL_OSCSRC_XTAL_SE))
    {
        if(!Device_verifyXTAL(DEVICE_OSCSRC_FREQ / 1000000))
        {
            //
            // The actual XTAL frequency does not match DEVICE_OSCSRC_FREQ!!
            // Please check the XTAL frequency used.
            //
            // By default, the Device_init function assumes 25MHz XTAL.
            // If a 20MHz crystal is used, please add a predefined symbol
            // "USE_20MHZ_XTAL" in your CCS project.
            // If a different XTAL is used, please update the DEVICE_SETCLOCK_CFG
            // macro accordingly.
            //
            // Note that the latest F2838x controlCARDs (Rev.B and later) have been
            // updated to use 25MHz XTAL by default. If you have an older 20MHz XTAL
            // controlCARD (E1, E2, or Rev.A), refer to the controlCARD
            // documentation on steps to reconfigure the controlCARD from 20MHz to
            // 25MHz.
            //
            ESTOP0;
            while(1);
        }
    }

    //
    // Set up PLL control and clock dividers
    //
    SysCtl_setClock(DEVICE_SETCLOCK_CFG);

    //
    // Make sure the LSPCLK divider is set to the default (divide by 4)
    //
    SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4);

    //
    // Set up AUXPLL control and clock dividers needed for CMCLK
    //
    SysCtl_setAuxClock(DEVICE_AUXSETCLOCK_CFG);

    //
    // Set up CMCLK to use AUXPLL as the clock source and set the
    // clock divider to 1.
    //
    SysCtl_setCMClk(SYSCTL_CMCLKOUT_DIV_1,SYSCTL_SOURCE_AUXPLL);

    // These asserts will check that the #defines for the clock rates in
    // device.h match the actual rates that have been configured. If they do
    // not match, check that the calculations of DEVICE_SYSCLK_FREQ,
    // DEVICE_LSPCLK_FREQ and DEVICE_AUXCLK_FREQ are accurate. Some
    // examples will not perform as expected if these are not correct.
    //
    ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
    ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
    ASSERT(SysCtl_getAuxClock(DEVICE_OSCSRC_FREQ) == DEVICE_AUXCLK_FREQ);

#ifndef _FLASH
    //
    // Call Device_cal function when run using debugger
    // This function is called as part of the Boot code. The function is called
    // in the Device_init function since during debug time resets, the boot code
    // will not be executed and the gel script will reinitialize all the
    // registers and the calibrated values will be lost.
    // Sysctl_deviceCal is a wrapper function for Device_Cal
    //
    SysCtl_deviceCal();
#endif

#endif

    //
    // Turn on all peripherals
    //
    Device_enableAllPeripherals();
    Device_initGPIO();
}

#ifdef CPU1
//*****************************************************************************
//
// Function to boot CPU2
// Available bootmodes :
//      - BOOTMODE_BOOT_TO_FLASH_SECTOR0
//      - BOOTMODE_BOOT_TO_FLASH_SECTOR4
//      - BOOTMODE_BOOT_TO_FLASH_SECTOR8
//      - BOOTMODE_BOOT_TO_FLASH_SECTOR13
//      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR0
//      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR4
//      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR8
//      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR13
//      - BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM
//      - BOOTMODE_BOOT_TO_M0RAM
//      - BOOTMODE_BOOT_TO_USEROTP
//
// Note that while using BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM,
// BOOTMODE_IPC_MSGRAM_COPY_LENGTH_xxxW must be ORed with the bootmode parameter
//
// This function must be called after Device_init function
//
//*****************************************************************************
void Device_bootCPU2(uint32_t bootmode)
{
    //
    // Configure the CPU1TOCPU2IPCBOOTMODE register
    //
    IPC_setBootMode(IPC_CPU1_L_CPU2_R,
                    (BOOT_KEY | CPU2_BOOT_FREQ_200MHZ | bootmode));

    //
    // Set IPC Flag 0
    //
    IPC_setFlagLtoR(IPC_CPU1_L_CPU2_R, IPC_FLAG0);

    //
    // Bring CPU2 out of reset. Wait for CPU2 to go out of reset.
    //
    SysCtl_controlCPU2Reset(SYSCTL_CORE_DEACTIVE);
    while(SysCtl_isCPU2Reset() == 0x1U);
}

//*****************************************************************************
//
// Function to boot CM
// Available bootmodes :
//      - BOOTMODE_BOOT_TO_FLASH_SECTOR0
//      - BOOTMODE_BOOT_TO_FLASH_SECTOR4
//      - BOOTMODE_BOOT_TO_FLASH_SECTOR8
//      - BOOTMODE_BOOT_TO_FLASH_SECTOR13
//      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR0
//      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR4
//      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR8
//      - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR13
//      - BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_S0RAM
//      - BOOTMODE_BOOT_TO_S0RAM
//      - BOOTMODE_BOOT_TO_USEROTP
//
// Note that while using BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM,
// BOOTMODE_IPC_MSGRAM_COPY_LENGTH_xxxW must be ORed with the bootmode parameter
//
// This function must be called after Device_init function
//
//*****************************************************************************
void Device_bootCM(uint32_t bootmode)
{
    //
    // Configure the CPU1TOCMIPCBOOTMODE register
    //
    IPC_setBootMode(IPC_CPU1_L_CM_R,
                    (BOOT_KEY | CM_BOOT_FREQ_125MHZ | bootmode));

    //
    // Set IPC Flag 0
    //
    IPC_setFlagLtoR(IPC_CPU1_L_CM_R, IPC_FLAG0);

    //
    // Bring CM out of reset. Wait for CM to go out of reset.
    //
    SysCtl_controlCMReset(SYSCTL_CORE_DEACTIVE);
    while(SysCtl_isCMReset() == 0x1U);
}
#endif

//*****************************************************************************
//
// Function to turn on all peripherals, enabling reads and writes to the
// peripherals' registers.
//
// Note that to reduce power, unused peripherals should be disabled.
//
//*****************************************************************************
void Device_enableAllPeripherals(void)
{

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CPUBGCRC);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1BGCRC);
#ifdef CPU1
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL);
#endif
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ERAD);

#ifdef CPU1
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2);
#endif

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM8);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM11);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM13);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM14);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM15);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM16);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP4);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP5);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP6);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP7);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP3);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD2);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCID);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIC);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPID);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANB);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPB);

#ifdef CPU1
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_USBA);
#endif

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS5);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS6);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS7);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS8);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACB);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACC);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB2);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB3);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB4);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB5);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB6);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB7);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB8);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSITXA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSITXB);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXB);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXC);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXD);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXE);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXF);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXG);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXH);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_PMBUSA);

#ifdef CPU1
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC0);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC2);

    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAT);
    
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCANA);

#endif

}

//*****************************************************************************
//
// Function to disable pin locks on GPIOs.
//
//*****************************************************************************
void Device_initGPIO(void)
{
    //
    // Disable pin locks.
    //
    GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF);
    GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF);
    GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF);
    GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF);
    GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF);
    GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF);

    //
    // Enable GPIO Pullups
    //
    Device_enableUnbondedGPIOPullups();
}

//*****************************************************************************
//
// Function to enable pullups for the unbonded GPIOs on the 176PTP package:
// GPIOs     Grp Bits
// 95-132    C   31
//           D   31:0
//           E   4:0
// 134-168   E   31:6
//           F   8:0
//
//*****************************************************************************

void Device_enableUnbondedGPIOPullupsFor176Pin(void)
{

    EALLOW;
    HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U;
    HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U;
    HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU;
    HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU;
    EDIS;
}

//*****************************************************************************
//
// Function to enable pullups for the unbonded GPIOs on the
// 176PTP package.
//
//*****************************************************************************
void Device_enableUnbondedGPIOPullups(void)
{
    //
    // bits 8-10 have pin count
    //
    uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) &
                          (uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >>
                         SYSCTL_PARTIDL_PIN_COUNT_S);

    /*
     * 6 = 176 pin
     * 7 = 337 pin
     */
    if (pinCount == 6)
    {
        Device_enableUnbondedGPIOPullupsFor176Pin();
    }
    else
    {
        //
        // Do nothing - this is 337 pin package
        //
    }
}

//*****************************************************************************
//
// Function to verify the XTAL frequency
// freq is the XTAL frequency in MHz
// The function return true if the the actual XTAL frequency matches with the
// input value
//
// Note that this function assumes that the PLL is not already configured and
// hence uses SysClk freq = 10MHz for DCC calculation
//
//*****************************************************************************
#ifdef CPU1
bool Device_verifyXTAL(float freq)
{
    //
    // Use DCC to verify the XTAL frequency using INTOSC2 as reference clock
    //

    //
    // Enable DCC0 clock
    //
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC0);

    //
    // Insert atleast 5 cycles delay after enabling the peripheral clock
    //
    asm(" RPT #5 || NOP");

    //
    // Configures XTAL as CLKSRC0 and INTOSC2 as CLKSRC1
    // Fclk0 = XTAL frequency (input parameter)
    // Fclk1 = INTOSC2 frequency = 10MHz
    //
    // Configuring DCC error tolerance of +/-1%
    // INTOSC2 can have a variance in frequency of +/-10%
    //
    // Assuming PLL is not already configured, SysClk freq = 10MHz
    //
    // Note : Update the tolerance and INTOSC2 frequency variance as necessary.
    //
    return (DCC_verifyClockFrequency(DCC0_BASE,
                                     DCC_COUNT1SRC_INTOSC2, 10.0F,
                                     DCC_COUNT0SRC_XTAL, freq,
                                     1.0F, 10.0F, 10.0F));

}
#endif


//*****************************************************************************
//
// Error handling function to be called when an ASSERT is violated
//
//*****************************************************************************
void __error__(char *filename, uint32_t line)
{
    //
    // An ASSERT condition was evaluated as false. You can use the filename and
    // line parameters to determine what went wrong.
    //
    ESTOP0;
}

[引用 userid="128297" url="~/support/icros/c2000-icro-group/c2f/c2000-icro-forum-forum/1071727/tms320f28388d-ice-possible to get－spurious－der-debugger-secture-se-outse-wrong－code-line/3971409#3971409]]]

您是否使用 SPI_enableHighSpeedMode()来启用高速模式？ 断言是否在该函数内导致问题？

[/引用]

根据 SPI 或 LSP 设置，我在 Board_init()；func 或 SPI_setConfig()；func 中得到断言错误。 我想将 SPI 设置为最大频率，而不会出现任何断言错误。

提前进行轮纳克。

谢谢，