[参考译文] TMS320F2.8386万D：接收nack后发送停止序列(主写入)

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1098581/tms320f28386d-sending-a-stop-sequence-after-receiving-nack-master-write

您好，

  我正在与 TMS320F2.8386万D进行I2C通信，我正在尝试实现 以下行为。

我希望I2C模块在出现nack'ed.消息后发送停止序列  目前我的代码只发送

停止成功写出所有字节的消息序列。  这对我所处的从属设备很重要  

正在写入，每条消息后都会出现停止序列，以便它识别我的重试。

  在TRM中，它对I2CMDR.STP寄存器进行了如下说明："... 设备已将STP设置为生成停止  

I2C模块的内部数据计数器倒计数到0英寸时的情况。  在TRM中，它还提到了  

I2CNT寄存器，"The value written to I2CCNT is copied to an internal data counter.  内部数据计数 器将递减

每个传输的字节由1 ... 如果在主模式(I2CMDR上的STP)中请求停止条件，I2C模块将终止

倒计时完成时的停止条件下的传输..."  我尝试利用这些点在我的中生成停止条件  

在一个nack后对机器进行状态。  非常感谢您的任何帮助，谢谢。 我在下面附上了我的代码片段。

switch(Substate)
{
	case -1:
	{      //NACK Detected

		EALLOW;
		I2caRegs->I2CSTR.bit.SCD = 1;
		I2caRegs->I2CMDR.bit.STP = 1; //Enabling the Stop condition upon CNT = 0;
		I2caRegs->I2CCNT = 0; //Trying to trick the I2C module that I have sent all of its bytes
		EDIS;

	
		if(masterWriteRetryCtr < masterWriteRetryLim)
		{
			//Code For Retry
			...
			//End Code For Retry
		}
		else
		{ 
			Substate = 0;
		}
		break;
	}
	 case 0:
	 {   // Master write complete.
		masterWriteRetryCtr = 0;
		break;
	 }
		
	 case 1:
	 {   // Transmit the next byte in Buffer, or end the master write process.
		 if ((I2caRegs->I2CSTR.bit.XRDY) || (I2caRegs->I2CSTR.bit.ARDY))
		 { //If its ready to send
			 if(I2caRegs->I2CSTR.bit.NACK)
			 {Substate = -1;}
			 else
			 {
				 I2caRegs->I2CDXR.all = Buffer[Ptr]; //Put next byte into transmit register
				 Ptr++;
			}
		 }
				 
		 if (I2caRegs->I2CSTR.bit.SCD == 1)
		 { //If Stop Condition
			 Substate = 0;
			 EALLOW;
			 I2caRegs->I2CSTR.bit.SCD = 1;
			 EDIS;}
			 break;
	 }
	 
	  case 2:
	  {   // Configure to be Master.
		  EALLOW;
		  Ptr = 0;
		  Substate = 1; 
		  I2caRegs->I2CCNT = ByteCount;       //NUMBER OF BYTES TRANSMITTING
		  I2caRegs->I2CMDR.bit.MST = 1;    	  //Master
		  I2caRegs->I2CMDR.bit.TRX = 1;       //Transmitting
		  I2caRegs->I2CMDR.bit.STP = 1;       //Send I2C STOP Sequence when CNT == 0
		  I2caRegs->I2CSTR.bit.SCD = 1;       // Clear any Detected Stops
		  I2caRegs->I2CMDR.bit.STT = 1;
		  EDIS;
		  break;
		  }
}