Other Parts Discussed in Thread: C2000WARE
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器件型号：TMS320F280025C 主题中讨论的其他器件：C2000WARE
您好！
我正在使用 SCI 引导加载程序示例编写我自己的解密引导加载程序。 到目前为止、我能够从闪存加载引导加载程序、并引导它
完成更新后的应用程序是可用的固件。 (例如、在 ：C：\ti\c2000\C2000Ware_4_00_00_00\driverlib\f28002x\examples\flash\ccs\flash_ex3_sci_flash_kernel.projectspec 中)
现在我添加了 AES 解密库、我注意到 、当我从 LCR main 而不是 LB _c_int00开始时、testVectorCBCArray 仅具有损坏的数据：
具有 testVectorCBCArray 的主函数：
//########################################################################### // // FILE: flash_kernel_ex3_sci_flash_kernel.c // // TITLE: Flash Programming Solution using SCI. // //! In this example, we set up a UART connection with a host using SCI, receive //! commands for CPU1 to perform which then sends ACK, NAK, and status packets //! back to the host after receiving and completing the tasks. This kernel has //! the ability to program, verify, unlock, reset, and run an application. //! Each command either expects no data from the command packet //! or specific data relative to the command. //! //! In this example, we set up a UART connection with a host using SCI, receive //! an application for CPU01 in -sci8 ascii format to run on the device and //! program it into Flash. // //########################################################################### // $Copyright: // Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### // // Included Files // #include <string.h> #include "flash_programming_f28002x.h" // Flash API example header file #include "F021_F28002x_C28x.h" #include "cpu1bootrom.h" #include "device.h" #include "flash.h" #include "gpio.h" #include "interrupt.h" #include "driverlib.h" #include "aes_cbc.h" #define USER_APPLICATION_BASE_ADDRESS 0x084000 // // Function Prototypes // void exampleError(Fapi_StatusType status); void initFlashSectors(void); extern uint32_t sciGetFunction(uint32_t BootMode); extern void sciaFlush(void); ////////////////////// // // Defines // #define TEST_PASS 0xABCDABCD #define TEST_FAIL 0xDEADDEAD // // Global Variables // // // Global error counter & status // uint16_t errCountGlobal = 0; uint32_t testStatusGlobal; // // Structure for AES CBC tests // typedef struct { AES_KeySize keySize; AES_OperationMode opMode; uint16_t keyArray[32]; uint16_t initVector[16]; uint16_t dataLength; uint16_t plainText[16]; uint16_t cipherText[16]; } testVectorCBC; // // Test Cases // static testVectorCBC testVectorCBCArray[2] = { // // Test Case #1 // { .keySize = AES_128, .opMode = AES_OPMODE_ENCRYPT, .keyArray = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}, .initVector = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}, .dataLength = 1, .plainText = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a}, .cipherText = {0x76, 0x49, 0xab, 0xac, 0x81, 0x19, 0xb2, 0x46, 0xce, 0xe9, 0x8e, 0x9b, 0x12, 0xe9, 0x19, 0x7d} }, // // Test Case #2 // { .keySize = AES_128, .opMode = AES_OPMODE_DECRYPT, .keyArray = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}, .initVector = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}, .dataLength = 1, .plainText = {0x76, 0x49, 0xab, 0xac, 0x81, 0x19, 0xb2, 0x46, 0xce, 0xe9, 0x8e, 0x9b, 0x12, 0xe9, 0x19, 0x7d}, .cipherText = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a} } }; ///////////////////// //#pragma CODE_SECTION(AES_performCBCFast, "AES_performCBCFast"); // // Main // uint32_t main(void) { // // flush SCIA TX port by waiting while it is busy, driverlib. // sciaFlush(); // // Step 1. Initialize System Control: // Enable Peripheral Clocks // Device_init(); // // Step 2. Initialize GPIO: // Device_initGPIO(); // // Step 3. Clear all interrupts and initialize PIE vector table: // Disable CPU interrupts // DINT; // // init interrupt and vectorTable, driverlib. // Interrupt_initModule(); Interrupt_initVectorTable(); // Disable CPU interrupts and clear all CPU interrupt flags: IER = 0x0000; IFR = 0x0000; Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, 4); initFlashSectors(); uint32_t EntryAddr = USER_APPLICATION_BASE_ADDRESS; uint32_t i = 0; for(i=0; i<3; i++) { // // Delay // // GPIO_togglePin(34); DEVICE_DELAY_US(1e6); GPIO_togglePin(31); } //////////////////////////////////////////////////////////////// uint16_t errCountLocal, cnt; uint16_t *keyArray, *initVector, dataLength; uint16_t *expCipherTextArray, *plainTextArray; uint16_t vectorCnt; AES_KeySize keySize; AES_OperationMode opMode; // // Initialize local variables. // errCountLocal = 0; // // Loop through all the given vectors. // for(vectorCnt = 0; vectorCnt < 2; vectorCnt++) { // // Get the current vector's data members. // keySize = testVectorCBCArray[vectorCnt].keySize; opMode = testVectorCBCArray[vectorCnt].opMode; keyArray = testVectorCBCArray[vectorCnt].keyArray; initVector = testVectorCBCArray[vectorCnt].initVector; dataLength = testVectorCBCArray[vectorCnt].dataLength; plainTextArray = testVectorCBCArray[vectorCnt].plainText; expCipherTextArray = testVectorCBCArray[vectorCnt].cipherText; // // Perform AES-CBC // AES_performCBC(plainTextArray, dataLength, keyArray, keySize, opMode, initVector); // // Check the results // for(cnt = 0; cnt < (dataLength * 16U); cnt++) { if(plainTextArray[cnt] != expCipherTextArray[cnt]) { errCountLocal++; } } // // Update the global error counter. // if(errCountLocal > 0) { errCountGlobal++; } // // Clear the local error counter. // errCountLocal = 0; } // // Update test status variable // if(errCountGlobal == 0) { testStatusGlobal = TEST_PASS; } else { testStatusGlobal = TEST_FAIL; } //////////////////////////////// // while(1) // { // GPIO_togglePin(34); // DEVICE_DELAY_US(1e5); // GPIO_togglePin(31); // } uint16_t *addr = USER_APPLICATION_BASE_ADDRESS; if(*addr != 0xFFFF) { return(EntryAddr); } else { EntryAddr = sciGetFunction(SCI_BOOT_ALT1); } return(EntryAddr); } // // initFlashSectors - Initialize flash API and active flash bank sectors // void initFlashSectors(void) { EALLOW; Fapi_StatusType oReturnCheck; oReturnCheck = Fapi_initializeAPI(F021_CPU0_BASE_ADDRESS, 100); if(oReturnCheck != Fapi_Status_Success) { exampleError(oReturnCheck); } oReturnCheck = Fapi_setActiveFlashBank(Fapi_FlashBank0); if(oReturnCheck != Fapi_Status_Success) { exampleError(oReturnCheck); } EDIS; } // // exampleError - For this example, if an error is found just stop here // #ifdef __TI_COMPILER_VERSION__ #if __TI_COMPILER_VERSION__ >= 15009000 #pragma CODE_SECTION(exampleError,".TI.ramfunc"); #else #pragma CODE_SECTION(exampleError,"ramfuncs"); #endif #endif void exampleError(Fapi_StatusType status) { // // Error code will be in the status parameter // __asm(" ESTOP0"); } // // End of file //
代码启动.asm：
;//########################################################################### ;// ;// FILE: flash_kernel_ex3_codestartbranch.asm ;// ;// TITLE: Branch for redirecting code execution after boot. ;// ;// For these examples, code_start is the first code that is executed after ;// exiting the boot ROM code. ;// ;// The codestart section in the linker cmd file is used to physically place ;// this code at the correct memory location. This section should be placed ;// at the location the BOOT ROM will re-direct the code to. For example, ;// for boot to FLASH this code will be located at 0x80000. ;// ;// In addition, the example f28002x projects are setup such that the codegen ;// entry point is also set to the codestart label. This is done by linker ;// option -e in the project build options. When the debugger loads the code, ;// it will automatically set the PC to the "entry point" address indicated by ;// the -e linker option. In this case the debugger is simply assigning the PC, ;// it is not the same as a full reset of the device. ;// ;// The compiler may warn that the entry point for the project is other then ;// _c_init00. _c_init00 is the C environment setup and is run before ;// main() is entered. The codestart code will re-direct the execution ;// to _c_init00 and thus there is no worry and this warning can be ignored. ;// ;//########################################################################### ;// $Copyright: ;// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ ;// ;// Redistribution and use in source and binary forms, with or without ;// modification, are permitted provided that the following conditions ;// are met: ;// ;// Redistributions of source code must retain the above copyright ;// notice, this list of conditions and the following disclaimer. ;// ;// Redistributions in binary form must reproduce the above copyright ;// notice, this list of conditions and the following disclaimer in the ;// documentation and/or other materials provided with the ;// distribution. ;// ;// Neither the name of Texas Instruments Incorporated nor the names of ;// its contributors may be used to endorse or promote products derived ;// from this software without specific prior written permission. ;// ;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;// $ ;//########################################################################### *********************************************************************** WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 .ref _c_int00 .ref main .global code_start .global ExitBoot *********************************************************************** * Function: codestart section * * Description: Branch to code starting point *********************************************************************** .sect "codestart" .retain code_start: .if WD_DISABLE == 1 LB wd_disable ;Branch to watchdog disable code .else LB _c_int00 ;Branch to start of boot._asm in RTS library ;LCR main .endif ;end codestart section *********************************************************************** * Function: wd_disable * * Description: Disables the watchdog timer *********************************************************************** .if WD_DISABLE == 1 .text wd_disable: SETC OBJMODE ;Set OBJMODE for 28x object code EALLOW ;Enable EALLOW protected register access MOVZ DP, #7029h>>6 ;Set data page for WDCR register MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD EDIS ;Disable EALLOW protected register access ;LB _c_int00 ;Branch to start of boot._asm in RTS library LCR main ; Cleanup and exit. At this point the EntryAddr ; is located in the ACC register BF ExitBoot, UNC .endif ;end wd_disable ;----------------------------------------------- ; ExitBoot ;----------------------------------------------- ;----------------------------------------------- ;This module cleans up after the boot loader ; ; 1) Make sure the stack is deallocated. ; SP = 0x400 after exiting the boot ; loader ; 2) Push 0 onto the stack so RPC will be ; 0 after using LRETR to jump to the ; entry point ; 2) Load RPC with the entry point ; 3) Clear all XARn registers ; 4) Clear ACC, P and XT registers ; 5) LRETR - this will also clear the RPC ; register since 0 was on the stack ;----------------------------------------------- ExitBoot: __stack: .usect ".stack",0 ;----------------------------------------------- ; Insure that the stack is deallocated ;----------------------------------------------- MOV SP,#__stack ;----------------------------------------------- ; Clear the bottom of the stack. This will endup ; in RPC when we are finished ;----------------------------------------------- MOV *SP++,#0 MOV *SP++,#0 ;----------------------------------------------- ; Load RPC with the entry point as determined ; by the boot mode. This address will be returned ; in the ACC register. ;----------------------------------------------- PUSH ACC POP RPC ;----------------------------------------------- ; Put registers back in their reset state. ; ; Clear all the XARn, ACC, XT, and P and DP ; registers ; ; NOTE: Leave the device in C28x operating mode ; (OBJMODE = 1, AMODE = 0) ;----------------------------------------------- ZAPA MOVL XT,ACC MOVZ AR0,AL MOVZ AR1,AL MOVZ AR2,AL MOVZ AR3,AL MOVZ AR4,AL MOVZ AR5,AL MOVZ AR6,AL MOVZ AR7,AL MOVW DP, #0 ;------------------------------------------------ ; Restore ST0 and ST1. Note OBJMODE is ; the only bit not restored to its reset state. ; OBJMODE is left set for C28x object operating ; mode. ; ; ST0 = 0x0000 ST1 = 0x0A0B ; 15:10 OVC = 0 15:13 ARP = 0 ; 9: 7 PM = 0 12 XF = 0 ; 6 V = 0 11 M0M1MAP = 1 ; 5 N = 0 10 reserved ; 4 Z = 0 9 OBJMODE = 1 ; 3 C = 0 8 AMODE = 0 ; 2 TC = 0 7 IDLESTAT = 0 ; 1 OVM = 0 6 EALLOW = 0 ; 0 SXM = 0 5 LOOP = 0 ; 4 SPA = 0 ; 3 VMAP = 1 ; 2 PAGE0 = 0 ; 1 DBGM = 1 ; 0 INTM = 1 ;----------------------------------------------- MOV *SP++,#0 MOV *SP++,#0x0A0B POP ST1 POP ST0 ;------------------------------------------------ ; Jump to the EntryAddr as defined by the ; boot mode selected and continue execution ;----------------------------------------------- LRETR ;eof ---------- .end ;// ;// End of file. ;//
链接器文件：
-stack 0x380
MEMORY
{
BEGIN : origin = 0x080000, length = 0x000002
BOOT_RSVD : origin = 0x00000002, length = 0x00000126
RAMM0 : origin = 0x00000128, length = 0x000002D8
RAMM1 : origin = 0x00000400, length = 0x000003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x000007F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
/* RAMLS4 : origin = 0x0000A000, length = 0x00000800
RAMLS5 : origin = 0x0000A800, length = 0x00000800
RAMLS6 : origin = 0x0000B000, length = 0x00000800
RAMLS7 : origin = 0x0000B800, length = 0x00000800*/
/* Combining all the LS RAMs */
RAMLS4567 : origin = 0x0000A000, length = 0x00002000
RAMGS0 : origin = 0x0000C000, length = 0x000007F8
// RAMGS0_RSVD : origin = 0x0000C7F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
BOOTROM : origin = 0x003F0000, length = 0x00008000
BOOTROM_EXT : origin = 0x003F8000, length = 0x00007FC0
RESET : origin = 0x003FFFC0, length = 0x00000002
/* Flash sectors */
/* BANK 0 */
FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE /* on-chip Flash */
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x000FF0 /* on-chip Flash */
// FLASH_BANK0_SEC15_RSVD : origin = 0x08FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
}
SECTIONS
{
.reset : > RESET, TYPE = DSECT /* not used, */
codestart : > BEGIN, ALIGN(4)
.TI.ramfunc : LOAD = (FLASH_BANK0_SEC0 | FLASH_BANK0_SEC1 | FLASH_BANK0_SEC2), /* This sector is loaded from flash to RAM */
RUN = RAMLS4567,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
.text : >> FLASH_BANK0_SEC0 | FLASH_BANK0_SEC1 | FLASH_BANK0_SEC2, ALIGN(8) /* Programm is in flash */
.cinit : > FLASH_BANK0_SEC2, ALIGN(4)
.switch : > FLASH_BANK0_SEC2, ALIGN(4)
.cio : > FLASH_BANK0_SEC2
.pinit : > FLASH_BANK0_SEC2 ALIGN(4)
.const : > FLASH_BANK0_SEC2, ALIGN(4)
.init_array : > FLASH_BANK0_SEC2, ALIGN(4)
.stack : > RAMM1
.bss : > RAMM0
.bss:output : > RAMM0
.bss:cio : > RAMM0
.data : > RAMM0 /* Seems not to work, when using AES data --> leads to CRC error while updating, why? */
.sysmem : > RAMM0
ramgs0 : > RAMGS0
/* Allocate IQ math areas: */
IQmath : > RAMM0
IQmathTables : > RAMM0
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
我真的不知道这是怎么发生的、除了从 LCR main 开始是 RAM 损坏。 是否有任何关于如何解决该问题的建议？
编辑：看来"LB _c_int00"执行一些基本的初始化、如下所述： https://downloads.ti.com/docs/esd/SPRUI03/the--c-int00-function-slau1312470.html。 那么、我的问题是、如何调整.asm 代码、我可以首先调用"LB _c_int00"、然后以某种方式将应用程序跳转地址推送到 ACC 寄存器、以便"ExitBoot"函数可以加载它以进行跳转？
