[参考译文] TMS320F28379D：使用 ADC 时 PWM 波形出现问题

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1060016/tms320f28379d-problem-in-pwm-waveform-while-using-adc

我希望通过以下方式生成相移 PWM 波形：

EPWM1A 和 EPWM1B -主器件；

EPWM2A 和 EPWM2B -由 EPWM1乘以 D1相移；

EPWM3 SOC A 用于触发 ADC 的 SOC。

EPWM4A 和 EPWM4B 通过 D 从 EPWM1相移；

EPWM5A 和 EPWM5B 由 D+D2从 EPWM1相移。

使用四个 ADC -  

ADCA2 -用于测量 D -存储在 ADCARESULT0中的结果-移动10个样本的平均滤波器-结果馈送到中断中的 EPWM4相位寄存器。

ADCB2 -用于测量 D1 -存储在 ADCBRESULT1中的结果-移动100个样本的平均滤波器-结果馈送到中断中的 EPWM1相位寄存器。

ADCA3 -用于测量 D2 -存储在 ADCARESULT2-移动100个样本的平均滤波器中的结果-结果被馈送到中断中的 ePWM 相位寄存器。

ADCB3 - 用于测量模式电流 -存储在 ADCBRESULT3中的结果。

一旦我尝试在一个特定电平之后根据 ADC 生成 PWM 波形、 噪声就会进入 PWM 波形 、这会在 某些瞬间导致 PWM 波形发生很大变化、从而在硬件中造成问题。 在 ADC 附近连接了100pF 滤波器。 当硬件在开环运行时、不会观察到这种现象。

代码附在此处。

//###########################################################################
//
// FILE:    epwm_deadband_c28.c
//
// TITLE:   Check PWM Dead-Band
//
//! \addtogroup cpu01_example_list
//! <h1> EPWM dead band control (epwm_deadband)</h1>
//!
//! During the test, monitor ePWM1, ePWM2, and/or ePWM3 outputs
//! on a scope.
//!
//! - ePWM1A is on GPIO0
//! - ePWM1B is on GPIO1
//! - ePWM2A is on GPIO2
//! - ePWM2B is on GPIO3
//! - ePWM3A is on GPIO4
//! - ePWM3B is on GPIO5
//!
//! This example configures ePWM1, ePWM2 and ePWM3 for:
//! - Count up/down
//! - Deadband
//!
//! 3 Examples are included:
//! - ePWM1: Active low PWMs
//! - ePWM2: Active low complementary PWMs
//! - ePWM3: Active high complementary PWMs
//!
//! Each ePWM is configured to interrupt on the 3rd zero event.
//! When this happens the deadband is modified such that
//! 0 <= DB <= DB_MAX.  That is, the deadband will move up and
//! down between 0 and the maximum value.
//!
//! View the EPWM1A/B, EPWM2A/B and EPWM3A/B waveforms
//! via an oscilloscope
//
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.12.00.00 $
// $Release Date: Fri Feb 12 19:03:23 IST 2021 $
// $Copyright:
// Copyright (C) 2013-2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"



//Defines
#define D12_BUFFER 200
#define D_BUFFER 20
#define EPWM_DB 100

//
//
//
// Globals
//
Uint16 Mode_current;
Uint16 D1;
Uint16 D2;
Uint16 D;
Uint32 D1_adcb1;
Uint32 D2_adcb2;
Uint32 D_adcb3;
Uint16 D1_adcbresult1[D12_BUFFER];
Uint16 D2_adcbresult2[D12_BUFFER];
Uint16 D_adcbresult3[D_BUFFER];
Uint16 indexD12;
Uint16 indexD;



//
// Function Prototypes
//Here for simple DAB we will use EPWM1, EPWM2, EPWM4, EPWM5, EPWM6

void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
void InitEPwm4Example(void);
void InitEPwm5Example(void);

void ConfigureADC(void);
void SetupADCSoftware(void);

__interrupt void adcb2_isr(void);


//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks


// This example function is found in the F2837xD_SysCtrl.c file.
//




    InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to its default state.
//
    InitGpio();


//
// enable PWM1, PWM2 and PWM3
//
    CpuSysRegs.PCLKCR2.bit.EPWM1=1;
    CpuSysRegs.PCLKCR2.bit.EPWM2=1;
    CpuSysRegs.PCLKCR2.bit.EPWM3=1;
    CpuSysRegs.PCLKCR2.bit.EPWM4=1;
    CpuSysRegs.PCLKCR2.bit.EPWM5=1;

//
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the F2837xD_EPwm.c file
//
    InitEPwm1Gpio();
    InitEPwm2Gpio();
    InitEPwm3Gpio();
    InitEPwm4Gpio();
    InitEPwm5Gpio();

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
    DINT;

//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
    InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
    IER = 0x0000;
    IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
    InitPieVectTable();

//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.ADCB2_INT = &adcb2_isr;
    EDIS;   // This is needed to disable write to EALLOW protected registers

//
// Step 4. Initialize the Device Peripherals:
//

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
    EDIS;


    InitEPwm1Example();
    InitEPwm2Example();
    InitEPwm3Example();
    InitEPwm4Example();
    InitEPwm5Example();



//
// Step 5. User specific code, enable interrupts:
// Initialize counters:
//

//
// Enable CPU INT10 which is connected to ADCB2 INT:
//

    IER |= M_INT10;

//
// Enable ADCB2 INTn in the PIE: Group 10 interrupt 6
//

    PieCtrlRegs.PIEIER10.bit.INTx6 = 1;

//
// Enable global Interrupts and higher priority real-time debug events:
//
    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global realtime interrupt DBGM


//
//
// Initialize results buffer
//
    for(indexD12 = 0; indexD12 < D12_BUFFER; indexD12++)
    {
        D1_adcbresult1[indexD12] = 0;
        D2_adcbresult2[indexD12] = 0;
    }
    for(indexD = 0; indexD < D_BUFFER; indexD++)
    {
        D_adcbresult3[indexD] = 0;
    }
     indexD12 = 0;
     indexD   = 0;
     D1_adcb1 = 2500;
     D2_adcb2 = 2500;
     D_adcb3 = 10;
     D1 = 2500;
     D2 = 2500;
     D = 10;

// Setup ADC

     ConfigureADC();
     SetupADCSoftware();

//
    //start ePWM
    //
    EPwm3Regs.ETSEL.bit.SOCAEN = 1;  //enable SOCA
    //EPwm3Regs.ETSEL.bit.SOCBEN = 1;  //enable SOCB
    EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; //unfreeze, and enter down count mode
    //EPwm1Regs.ETSEL.bit.SOCAEN = 1;  //enable SOCA
    //EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; //unfreeze, and enter down count mode

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
    EDIS;
//
// Step 6. IDLE loop. Just sit and loop forever (optional):
//
    do
        {
            //
            // Wait while ePWM causes ADC conversions.
            // ADCA1 ISR processes each new set of conversions.
            //
        }
        while(1);
}


//
// adcb2_isr
//
__interrupt void adcb2_isr(void)
 {
     Uint16 i;

     D_adcbresult3[indexD++] = AdcaResultRegs.ADCRESULT0;
     D1_adcbresult1[indexD12] = AdcbResultRegs.ADCRESULT2;
     D2_adcbresult2[indexD12++] = AdcaResultRegs.ADCRESULT1;
     Mode_current  = AdcbResultRegs.ADCRESULT3;

     if (indexD12 >= D12_BUFFER)
     {   indexD12 = 0;

         D1_adcb1 = 0;
         D2_adcb2 = 0;

         for(i = 0; i < D12_BUFFER; i++)
         {D1_adcb1 = D1_adcb1 + D1_adcbresult1[i];
          D2_adcb2 = D2_adcb2 + D2_adcbresult2[i];
         }
     }

         D1 = D1_adcb1*0.005*0.916;
         D2 = D2_adcb2*0.005*0.916;



    //Limiter for D1 and D2
    if (D1 < 1000)
    {D1 = 1000;
    }
    else if (D1 > 2500)
    {D1 = 2500;
    }

    if (D2 < 1000)
    {D2 = 1000;
    }
    else if (D2 > 2500)
    {D2 = 2500;
    }


     if (indexD >= D_BUFFER)
      {  indexD = 0;

     D_adcb3 = 0;

         for(i = 0; i < D_BUFFER; i++)
           {D_adcb3 = D_adcb3 + D_adcbresult3[i];
           }
      }

      // 0.36632 is the calculated factor required to match the adcin results and TBPHS register
     if (Mode_current > 1000)
     { D = D_adcb3*0.05 * 0.36632;;
     if (D > 1125)
     {D =1125;
     }}
     else
     { D = 4999-(D_adcb3*0.05 * 0.36632);;
     if (D < 4249)
     {D =4249;
     }}

    EPwm2Regs.TBPHS.bit.TBPHS = D1;
    EPwm4Regs.TBPHS.bit.TBPHS = D;
    EPwm5Regs.TBPHS.bit.TBPHS = D+D2;
    //EPwm6Regs.TBPHS.bit.TBPHS = D2;

     //
     // Clear INT flag for this timer
     //
         AdcbRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //clear INT2 flag
     //
     //


    //
    // Acknowledge this interrupt to receive more interrupts from group 3
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
}

//
// InitEPwm1Example - Initialize EPWM1 configuration
//
void InitEPwm1Example()
{
    EPwm1Regs.TBPRD = 4999;                       // Set timer period
    EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
    EPwm1Regs.TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; // Count down
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;

    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm1Regs.CMPA.bit.CMPA = 2500;

    //
    // Set actions
    //
    EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM1A on CMPA and reset at ZRO
    EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;

    //
    // Active High Complementary
    //
    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;      // Disable deadband since gate driver have its own
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm1Regs.DBRED.bit.DBRED = EPWM_DB;
    EPwm1Regs.DBFED.bit.DBFED = EPWM_DB;

/*    //
       // start SOC
       //
        EPwm1Regs.ETSEL.bit.SOCAEN    = 0;    // Disable SOC on A group
        EPwm1Regs.ETSEL.bit.SOCASEL   = 5;   // Select SOC on down-count
        EPwm1Regs.ETPS.bit.SOCAPRD    = 1;       // Generate pulse on 1st event
        EPwm1Regs.TBCTL.bit.CTRMODE   = TB_FREEZE; // FREEZE
*/

}

//
// InitEPwm2Example - Initialize EPWM2 configuration
//
void InitEPwm2Example()
{
    EPwm2Regs.TBPRD = 4999;                       // Set timer period
    EPwm2Regs.TBPHS.bit.TBPHS = 2500;               // Phase is 0
    EPwm2Regs.TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; // Count down
    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm2Regs.CMPA.bit.CMPA = 2500;

    //
    // Set actions
    //
    EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM2A on Zero
    EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;

    //
    // Active High Complementary
    //
    EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm2Regs.DBRED.bit.DBRED = EPWM_DB;
    EPwm2Regs.DBFED.bit.DBFED = EPWM_DB;
}

// EPWM3 will be unused.
// InitEPwm3Example - Initialize EPWM2 configuration
//
void InitEPwm3Example()
{
    EPwm3Regs.TBPRD = 1249;                       // Set timer period
    EPwm3Regs.TBPHS.bit.TBPHS = 0x0000;                // Phase is 0
    EPwm3Regs.TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

    EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm3Regs.CMPA.bit.CMPA = 625;

    //
    // Set actions
    //
    EPwm3Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM1A on Zero
    EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;

    //
    // Active High Complementary
    //
    EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
    //EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    //EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    //EPwm3Regs.DBRED.bit.DBRED = EPWM_DB;
    //EPwm3Regs.DBFED.bit.DBFED = EPWM_DB;

    //
   // start SOC
   //
    EPwm3Regs.ETSEL.bit.SOCAEN    = 0;    // Disable SOC on A group
    EPwm3Regs.ETSEL.bit.SOCASEL    = 5;   // Select SOC on down-count
    EPwm3Regs.ETPS.bit.SOCAPRD = 1;       // Generate pulse on 1st event
    EPwm3Regs.TBCTL.bit.CTRMODE = TB_FREEZE; // FREEZE
}

//
// InitEPwm4Example - Initialize EPWM2 configuration
//
void InitEPwm4Example()
{
    SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN = 0;   //EPWM1SYNCOUT
    EPwm4Regs.TBPRD = 4999;                       // Set timer period
    EPwm4Regs.TBPHS.bit.TBPHS = 0;           // Phase is D
    EPwm4Regs.TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; // Count down
    EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;   //It should be set to zero

    EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm4Regs.CMPA.bit.CMPA = 2500;

    //
    // Set actions
    //
    EPwm4Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM4A on Zero
    EPwm4Regs.AQCTLA.bit.CAD = AQ_SET;


    //
    // Active High Complementary
    //
    EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm4Regs.DBRED.bit.DBRED = EPWM_DB;
    EPwm4Regs.DBFED.bit.DBFED = EPWM_DB;
}

//
// InitEPwm5Example - Initialize EPWM2 configuration
//
void InitEPwm5Example()
{
    EPwm5Regs.TBPRD = 4999;                       // Set timer period
    EPwm5Regs.TBPHS.bit.TBPHS = 0;               // Phase is D
    EPwm5Regs.TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN;  // Count down
    EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;

    EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm5Regs.CMPA.bit.CMPA = 2500;

    //
    // Set actions
    //
    EPwm5Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM1A on Zero
    EPwm5Regs.AQCTLA.bit.CAD = AQ_SET;

    //
    // Active High Complementary
    //
    EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm5Regs.DBRED.bit.DBRED = EPWM_DB;                 //2 us..... since EPWMCLK = TBCLK/1
    EPwm5Regs.DBFED.bit.DBFED = EPWM_DB;
}


void ConfigureADC(void)
{
    EALLOW;

    //
    //write configurations
    //

    AdcbRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
    AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
    AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
    AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

    //
    //Set pulse positions to late
    //
    AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
    AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;

    //
    //power up the ADCs
    //
    AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
    AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;

    //
    //delay for 1ms to allow ADC time to power up
    //
    DELAY_US(1000);

    EDIS;
}

//
// SetupADCSoftware - Setup ADC channels and acquisition window
//
void SetupADCSoftware(void)
{
    Uint16 acqps;

    //
    // Determine minimum acquisition window (in SYSCLKS) based on resolution
    //
    if(ADC_RESOLUTION_12BIT == AdcbRegs.ADCCTL2.bit.RESOLUTION)
    {
        acqps = 20; //75ns
    }
    else //resolution is 16-bit
    {
        acqps = 63; //320ns
    }

    if(ADC_RESOLUTION_12BIT == AdcaRegs.ADCCTL2.bit.RESOLUTION)
        {
            acqps = 20; //75ns
        }
        else //resolution is 16-bit
        {
            acqps = 63; //320ns
        }

    //
    //Select the channels to convert and end of conversion flag
    //ADCB
    //
    EALLOW;
    AdcaRegs.ADCSOC0CTL.bit.CHSEL = 2;  //SOC0 will convert pin A2
    AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is acqps +
    AdcaRegs.ADCSOC0CTL.bit.TRIGSEL =9;     //1 SYSCLK cycles

    AdcaRegs.ADCSOC1CTL.bit.CHSEL = 3;  //SOC1 will convert pin A3
    AdcaRegs.ADCSOC1CTL.bit.ACQPS = acqps; //sample window is acqps +
    AdcaRegs.ADCSOC1CTL.bit.TRIGSEL =9;     //1 SYSCLK cycles

    AdcbRegs.ADCSOC2CTL.bit.CHSEL = 2;  //SOC2 will convert pin B2
    AdcbRegs.ADCSOC2CTL.bit.ACQPS = acqps; //sample window is acqps +
    AdcbRegs.ADCSOC2CTL.bit.TRIGSEL =9;     //1 SYSCLK cycles

    AdcbRegs.ADCSOC3CTL.bit.CHSEL = 3;  //SOC2 will convert pin B3
    AdcbRegs.ADCSOC3CTL.bit.ACQPS = acqps; //sample window is acqps +
    AdcbRegs.ADCSOC3CTL.bit.TRIGSEL =9;     //1 SYSCLK cycles


    AdcbRegs.ADCINTSEL1N2.bit.INT2SEL = 0x3; //end of SOC1 of Adcb will set INT2 flag
    AdcbRegs.ADCINTSEL1N2.bit.INT2E = 1;   //enable INT2 flag
    AdcbRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //make sure INT2 flag is cleared
    EDIS;
}
//
// End of file
//

我真的很痛苦。 希望你们能在这方面帮助我！！ 提前感谢
Sayandev